DS001 Datasheet, PDF (59/99 Pages) Xilinx, Inc – Spartan-II FPGA Family

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Spartan-II FPGA Family: DC and Switching Characteristics
IOB Output Delay Adjustments for Different Standards⁽¹⁾
Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust
the delays by the values shown. A delay adjusted in this way constitutes a worst-case limit.
Speed Grade
Symbol
Description
Standard
-6
-5
Units
Output Delay Adjustments (Adj)
T_{OLVTTL_S2}
Standard-specific adjustments for LVTTL, Slow, 2 mA
14.2
16.9
ns
T_{OLVTTL_S4}
output delays terminating at pads
(based on standard capacitive
4 mA
7.2
8.6
ns
T_{OLVTTL_S6}
load, C_SL)
6 mA
4.7
5.5
ns
T_{OLVTTL_S8}
8 mA
2.9
3.5
ns
T_{OLVTTL_S12}
12 mA
1.9
2.2
ns
T_{OLVTTL_S16}
16 mA
1.7
2.0
ns
T_{OLVTTL_S24}
24 mA
1.3
1.5
ns
T_{OLVTTL_F2}
LVTTL, Fast, 2 mA
12.6
15.0
ns
T_{OLVTTL_F4}
4 mA
5.1
6.1
ns
T_{OLVTTL_F6}
6 mA
3.0
3.6
ns
T_{OLVTTL_F8}
8 mA
1.0
1.2
ns
T_{OLVTTL_F12}
12 mA
0
0
ns
T_{OLVTTL_F16}
16 mA
–0.1
–0.1
ns
T_{OLVTTL_F24}
24 mA
–0.1
–0.2
ns
T_OLVCMOS2
LVCMOS2
0.2
0.2
ns
T_{OPCI33_3}
PCI, 33 MHz, 3.3V
2.4
2.9
ns
T_{OPCI33_5}
PCI, 33 MHz, 5.0V
2.9
3.5
ns
T_{OPCI66_3}
PCI, 66 MHz, 3.3V
–0.3
–0.4
ns
T_OGTL
GTL
0.6
0.7
ns
T_OGTLP
GTL+
0.9
1.1
ns
T_{OHSTL_I}
HSTL I
–0.4
–0.5
ns
T_{OHSTL_III}
HSTL III
–0.8
–1.0
ns
T_{OHSTL_IV}
HSTL IV
–0.9
–1.1
ns
T_{OSSTL2_I}
SSTL2 I
–0.4
–0.5
ns
T_{OSSLT2_II}
SSTL2 II
–0.8
–1.0
ns
T_{OSSTL3_I}
SSTL3 I
–0.4
–0.5
ns
T_{OSSTL3_II}
SSTL3 II
–0.9
–1.1
ns
T_OCTT
CTT
–0.5
–0.6
ns
T_OAGP
AGP
–0.8
–1.0
ns
Notes:
1. Output timing is measured at 1.4V with 35 pF external capacitive load for LVTTL. For other I/O standards and different loads, see the
tables "Constants for Calculating TIOOP" and "Delay Measurement Methodology," page 60.
1
DS001-3 (v2.8) June 13, 2008
Product Specification
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