DS001 Datasheet, PDF (80/99 Pages) Xilinx, Inc – Spartan-II FPGA Family

R
Spartan-II FPGA Family: Pinout Tables
XC2S50 Device Pinouts (Continued)
Additional XC2S50 Package Pins
XC2S50 Pad Name
Bndry
Function Bank TQ144 PQ208 FG256 Scan
TQ144
Not Connected Pins
I/O
0
-
-
D8
83
P104 P105
-
-
-
-
11/02/00
I/O
0
-
P188
A6
86
I/O, V_REF
GND
0
P12
P189
B7
89
-
-
P190 GND*
-
I/O
0
-
P191
C8
92
I/O
0
-
P192
D7
95
I/O
0
-
P193
E7
98
I/O
0
P11
P194
C7
104
I/O
0
P10
P195
B6
107
V_CCINT
V_CCO
-
P9
P196 V_CCINT*
-
0
-
P197 V_CCO
-
Bank 0*
GND
-
P8
P198 GND*
-
I/O
0
P7
P199
A5
110
I/O
0
P6
P200
C6
113
I/O
0
-
P201
B5
116
I/O
0
-
-
D6
119
I/O
0
-
P202
A4
122
I/O, V_REF
GND
0
P5
P203
B4
125
-
-
-
GND*
-
I/O
0
-
P204
E6
128
I/O
0
-
-
D5
131
I/O
0
P4
P205
A3
134
I/O
0
-
-
C5
137
I/O
0
P3
P206
B3
140
TCK
-
P2
P207
C4
-
V_CCO
0
P1
P208 V_CCO
-
Bank 0*
V_CCO
04/18/01
7
P144 P208 V_CCO
-
Bank 7*
Notes:
1. IRDY and TRDY can only be accessed when using Xilinx PCI
cores.
2. Pads labelled GND*, V_CCINT*, V_CCO Bank 0*, V_CCO Bank 1*,
V_CCO Bank 2*, V_CCO Bank 3*, V_CCO Bank 4*, V_CCO Bank 5*,
V_CCO Bank 6*, V_CCO Bank 7* are internally bonded to
independent ground or power planes within the package.
3. See "VCCO Banks" for details on V_CCO banking.
DS001-4 (v2.8) June 13, 2008
Product Specification
www.xilinx.com
Module 4 of 4
80