DS001 Datasheet, PDF (52/99 Pages) Xilinx, Inc – Spartan-II FPGA Family

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Spartan-II FPGA Family: DC and Switching Characteristics
Recommended Operating Conditions
Symbol
Description
Min
Max
Units
T_J
Junction temperature⁽¹⁾
Commercial
0
85
°C
Industrial
–40
100
°C
V_CCINT
Supply voltage relative to GND^(2,5) Commercial
2.5 – 5% 2.5 + 5%
V
Industrial
2.5 – 5% 2.5 + 5%
V
V_CCO
Supply voltage relative to GND^(3,5) Commercial
1.4
3.6
V
Industrial
1.4
3.6
V
T_IN
Input signal transition time⁽⁴⁾
-
250
ns
Notes:
1. At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.35% per °C.
2. Functional operation is guaranteed down to a minimum V_CCINT of 2.25V (Nominal V_CCINT – 10%). For every 50 mV reduction in
V_CCINT below 2.375V (nominal V_CCINT – 5%), all delay parameters increase by 3%.
3. Minimum and maximum values for V_CCO vary according to the I/O standard selected.
4. Input and output measurement threshold is ~50% of V_CCO. See "Delay Measurement Methodology," page 60 for specific levels.
5. Supply voltages may be applied in any order desired.
DC Characteristics Over Operating Conditions
Symbol
Description
Min
Typ
Max Units
V_DRINT Data Retention V_CCINT voltage (below which configuration data
2.0
-
may be lost)
-
V
V_DRIO Data Retention V_CCO voltage (below which configuration data may 1.2
-
be lost)
-
V
I_CCINTQ Quiescent V_CCINT supply current⁽¹⁾ XC2S15 Commercial
-
10
30
mA
Industrial
-
10
60
mA
XC2S30 Commercial
-
10
30
mA
Industrial
-
10
60
mA
XC2S50 Commercial
-
12
50
mA
Industrial
-
12
100
mA
XC2S100 Commercial
-
12
50
mA
Industrial
-
12
100
mA
XC2S150 Commercial
-
15
50
mA
Industrial
-
15
100
mA
XC2S200 Commercial
-
15
75
mA
Industrial
-
15
150
mA
I_CCOQ
I_REF
I_L
C_IN
Quiescent V_CCO supply current⁽¹⁾
V_REF current per V_REF pin
Input or output leakage current⁽²⁾
Input capacitance (sample tested)
VQ, CS, TQ, PQ, FG
packages
-
-
2
mA
-
-
20
μA
–10
-
+10
μA
-
-
8
pF
I_RPU
Pad pull-up (when selected) @ V_IN = 0V, V_CCO = 3.3V
(sample tested)⁽³⁾
-
-
0.25
mA
I_RPD
Pad pull-down (when selected) @ V_IN = 3.6V (sample tested)⁽³⁾
-
-
0.15
mA
Notes:
1. With no output current loads, no active input pull-up resistors, all I/O pins 3-stated and floating.
2. The I/O leakage current specification applies only when the V_CCINT and V_CCO supply voltages have reached their respective
minimum Recommended Operating Conditions.
3. Internal pull-up and pull-down resistors guarantee valid logic levels at unconnected input pins. These pull-up and pull-down resistors
do not provide valid logic levels when input pins are connected to other circuits.
DS001-3 (v2.8) June 13, 2008
Product Specification
www.xilinx.com
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