COP8AME9_14 Datasheet, PDF (93/102 Pages) Texas Instruments – COP8AME9 8-Bit CMOS Flash Microcontroller with 8k Memory, Dual Op Amps, Virtual EEPROM, Temperature Sensor, 10-Bit A/D and Brownout Reset

COP8AME9, COP8ANE9
www.ti.com
SNOS930F – MARCH 2001 – REVISED MARCH 2013
Table 43. OPCODE TABLE⁽¹⁾
Upper Nibble
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
JP−15 JP−31 LD 0F0,#i DRSZ
0F0
RRCA
RC ADC A,#i ADC IFBIT ANDSZ LD B,#0F IFBNE 0
JSR
JMP
JP+17 INTR 0
A,[B] 0,[B]
A,#i
x000–x0FF x000–x0FF
JP−14 JP−30 LD 0F1,#i DRSZ
*
SC
SUBC SUBC IFBIT JSRB LD B,#0E IFBNE 1
JSR
JMP
JP+18 JP+2 1
0F1
A,#i
A,[B] 1,[B]
x100–x1FF x100–x1FF
JP−13 JP−29 LD 0F2,#i DRSZ X A,[X+]
X IFEQ A,#i IFEQ IFBIT
Re- LD B,#0D IFBNE 2
JSR
JMP
JP+19 JP+3 2
0F2
A,[B+]
A,[B] 2,[B] served
x200–x2FF x200–x2FF
JP−12 JP−28 LD 0F3,#i DRSZ X A,[X−]
X IFGT A,#i IFGT IFBIT
Re- LD B,#0C IFBNE 3
JSR
JMP
JP+20 JP+4 3
0F3
A,[B−]
A,[B] 3,[B] served
x300–x3FF x300–x3FF
JP−11 JP−27 LD 0F4,#i DRSZ
0F4
VIS
LAID ADD A,#i ADD IFBIT CLRA LD B,#0B IFBNE 4
JSR
JMP
JP+21 JP+5 4
A,[B] 4,[B]
x400–x4FF x400–x4FF
JP−10 JP−26 LD 0F5,#i DRSZ
0F5
RPND
JID AND A,#i AND IFBIT SWAPA LD B,#0A IFBNE 5
JSR
JMP
JP+22 JP+6 5
A,[B] 5,[B]
x500–x5FF x500–x5FF
JP−9 JP−25 LD 0F6,#i DRSZ X A,[X] X A,[B] XOR A,#i XOR IFBIT DCORA LD B,#09 IFBNE 6
JSR
JMP
JP+23 JP+7 6
0F6
A,[B] 6,[B]
x600–x6FF x600–x6FF
JP−8 JP−24 LD 0F7,#i DRSZ
*
0F7
*
OR A,#i OR IFBIT PUSHA LD B,#08 IFBNE 7
JSR
JMP
JP+24 JP+8 7
A,[B] 7,[B]
x700–x7FF x700–x7FF
JP−7 JP−23 LD 0F8,#i DRSZ
0F8
NOP
RLCA LD A,#i IFC
SBIT
0,[B]
RBIT LD B,#07 IFBNE 8
JSR
JMP
JP+25 JP+9 8
0,[B]
x800–x8FF x800–x8FF
JP−6 JP−22 LD 0F9,#i DRSZ
0F9
IFNE
A,[B]
IFEQ IFNE A,#i IFNC SBIT
Md,#i
1,[B]
RBIT LD B,#06 IFBNE 9
JSR
JMP
JP+26 JP+10 9
1,[B]
x900–x9FF x900–x9FF
JP−5 JP−21
LD
0FA,#i
DRSZ LD A,[X+] LD
0FA
A,[B+]
LD
[B+],#i
INCA
SBIT
2,[B]
RBIT LD B,#05 IFBNE 0A
JSR
JMP
JP+27 JP+11 A
2,[B]
xA00–xAFF xA00–xAFF
JP−4 JP−20
LD
0FB,#i
DRSZ LD A,[X−] LD
LD
DECA SBIT
0FB
A,[B−] [B−],#i
3,[B]
RBIT LD B,#04 IFBNE 0B
JSR
JMP
JP+28 JP+12 B
3,[B]
xB00–xBFF xB00–xBFF
JP−3 JP−19
LD
0FC,#i
DRSZ LD Md,#i JMPL X A,Md POPA SBIT
0FC
4,[B]
RBIT LD B,#03 IFBNE 0C
JSR
JMP
JP+29 JP+13 C
4,[B]
xC00–xCFF xC00–xCFF
JP−2 JP−18
LD
0FD,#i
DRSZ
0FD
DIR
JSRL LD A,Md RETSK SBIT
RBIT LD B,#02 IFBNE 0D
JSR
JMP
JP+30 JP+14 D
5,[B]
5,[B]
xD00–xDFF xD00–xDFF
JP−1 JP−17
LD
0FE,#i
DRSZ LD A,[X] LD LD [B],#i RET
0FE
A,[B]
SBIT
6,[B]
RBIT LD B,#01 IFBNE 0E
JSR
JMP
JP+31 JP+15 E
6,[B]
xE00–xEFF xE00–xEFF
JP−0 JP−16
LD
DRSZ
*
0FF,#i
0FF
*
LD B,#i RETI SBIT RBIT LD B,#00 IFBNE 0F
JSR
JMP
JP+32 JP+16 F
7,[B]
7,[B]
xF00–xFFF xF00–xFFF
(1) * is an unused opcode; i is the immediate data; Md is a directly addressed memory location; The opcode 60 Hex is also the opcode for IFBIT #i,A
Copyright © 2001–2013, Texas Instruments Incorporated
Product Folder Links: COP8AME9 COP8ANE9
Submit Documentation Feedback
93