COP8AME9_14 Datasheet, PDF (69/102 Pages) Texas Instruments – COP8AME9 8-Bit CMOS Flash Microcontroller with 8k Memory, Dual Op Amps, Virtual EEPROM, Temperature Sensor, 10-Bit A/D and Brownout Reset

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Interrupts
SNOS930F – MARCH 2001 – REVISED MARCH 2013
INTRODUCTION
The device supports fourteen vectored interrupts. Interrupt sources include Timer 1, Timer 2, Timer 3, Timer T0,
Port L Wake-up, Software Trap, MICROWIRE/PLUS, USART and External Input.
All interrupts force a branch to location 00FF Hex in program memory. The VIS instruction may be used to vector
to the appropriate service routine from location 00FF Hex.
The Software trap has the highest priority while the default VIS has the lowest priority.
Each of the 13 maskable inputs has a fixed arbitration ranking and vector.
Figure 33 shows the Interrupt block diagram.
Figure 33. Interrupt Block Diagram
MASKABLE INTERRUPTS
All interrupts other than the Software Trap are maskable. Each maskable interrupt has an associated enable bit
and pending flag bit. The pending bit is set to 1 when the interrupt condition occurs. The state of the interrupt
enable bit, combined with the GIE bit determines whether an active pending flag actually triggers an interrupt. All
of the maskable interrupt pending and enable bits are contained in mapped control registers, and thus can be
controlled by the software.
A maskable interrupt condition triggers an interrupt under the following conditions:
1. The enable bit associated with that interrupt is set.
2. The GIE bit is set.
3. The device is not processing a non-maskable interrupt. (If a non-maskable interrupt is being serviced, a
maskable interrupt must wait until that service routine is completed.)
An interrupt is triggered only when all of these conditions are met at the beginning of an instruction. If different
maskable interrupts meet these conditions simultaneously, the highest-priority interrupt will be serviced first, and
the other pending interrupts must wait.
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