COP8AME9_14 Datasheet, PDF (34/102 Pages) Texas Instruments – COP8AME9 8-Bit CMOS Flash Microcontroller with 8k Memory, Dual Op Amps, Virtual EEPROM, Temperature Sensor, 10-Bit A/D and Brownout Reset

COP8AME9, COP8ANE9
SNOS930F – MARCH 2001 – REVISED MARCH 2013
www.ti.com
Figure 16. Functional Block Diagram for Idle Timer T0
ITSEL2
0
0
0
0
1
1
1
1
ITSEL1
0
0
1
1
0
0
1
1
Table 16. Idle Timer Window Length
ITSEL0
0
1
0
1
0
1
0
1
Idle Timer Period
High Speed
Mode
Dual Clock or
Low Speed Mode
4,096 inst. cycles
0.125 seconds
8,192 inst. cycles
0.25 seconds
16,384 inst. cycles
0.5 seconds
32,768 inst. cycles
1 second
65,536 inst. cycles
2 seconds
Reserved - Undefined
Reserved - Undefined
Reserved - Undefined
The ITSEL bits of the ITMR register are cleared on Reset and the Idle Timer period is reset to 4,096 instruction
cycles.
ITMR Register
LSON
HSON
DCEN
CCK
SEL
Bit 7
Bit 6
Bit 5
Bit 4
Bits 7–4: Described in Power Saving Features.
RSVD
Bit 3
ITSEL2
Bit 2
ITSEL1
Bit 1
ITSEL0
Bit 0
Note: Documentation for previous COP8 devices, which included the Programmable Idle Timer, recommended
the user write zero to the high order bits of the ITMR Register. If existing programs are updated to use this
device, writing zero to these bits will cause the device to reset (see Power Saving Features).
RSVD: This bit is reserved and must be set to 0.
ITSEL2:0: Selects the Idle Timer period as described in Table 16, Idle Timer Window Length.
Any time the IDLE Timer period is changed there is the possibility of generating a spurious IDLE Timer interrupt
by setting the T0PND bit. The user is advised to disable IDLE Timer interrupts prior to changing the value of the
ITSEL bits of the ITMR Register and then clear the T0PND bit before attempting to synchronize operation to the
IDLE Timer.
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