COP8AME9_14 Datasheet, PDF (64/102 Pages) Texas Instruments – COP8AME9 8-Bit CMOS Flash Microcontroller with 8k Memory, Dual Op Amps, Virtual EEPROM, Temperature Sensor, 10-Bit A/D and Brownout Reset

COP8AME9, COP8ANE9
SNOS930F – MARCH 2001 – REVISED MARCH 2013
www.ti.com
Table 32. Programmable Gain Amplifier Settling Times (continued)
GAIN
10
20
49
98
Open Loop
Time Constant (τ)
0.7µs
2 µs
3.2 µs
5.8 µs
N/A
Settling Time (7.6 * τ)
5 µs
16 µs
25 µs
45 µs
1050 µs
Programmable Gain Amplifier Offset Calibration
The programmable gain amplifier has an offset that could be as high as ± 7 mV. When using this amplifier, a
user may want to nullify this offset to obtain more accurate measurements with the A/D converter. Since this
amplifier has both an N channel and P channel pair on its input stage, it's necessary to adjust both pairs. This is
done with the use of two volatile registers, AMPTRMN and AMPTRMP, and some on-chip circuits. The two trim
registers will allow for trimming out the offset in 0.5 mV steps in either direction. Once the amplifier is trimmed,
the trim values are stored in AMPTRMN and AMPTRMP. Retrimming is necessary after any type of Reset.
These two registers are initialized to 040 (hex) on a Reset.
Table 33. AMPTRMN
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CALN
ATRMN6
ATRMN5
ATRMN4
ATRMN3
ATRMN2
ATRMN1
ATRMN0
CALN Enables the internal reference, VREFN, for trimming the N channel pair. Enabled = 1, Disabled = 0. This
bit, when = 1, also disables the analog multiplexor. To perform the trimming algorithm, the TRIM bit must
also = 1.
ATRMN6:0 Trim bits used for actual trimming. It uses a signed magnitude method. ATRMN6 is the sign bit.
When ATRMN6 = 1, it compensates for positive offset. When ATRMN6 = 0, it compensates for negative
offset. ATRMN5:0 are the magnitude of the trim with 000000 = no trim value and 111111 = highest trim
value.
Table 34. AMPTRMP
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CALP
ATRMP6
ATRMP5
ATRMP4
ATRMP3
ATRMP2
ATRMP1
ATRMP0
CALP Enables the internal reference, VREFP, for trimming the P channel pair. Enabled = 1, Disabled =0. This
bit, when = 1, also disables the analog multiplexor. To perform the trimming algorithm, the TRIM bit must
also = 1.
ATRMNP6:0 Trim bits used for actual trimming. It uses a signed magnitude method. ATRMP6 is the sign bit.
When ATRMP6 = 1, it compensates for positive offset. When ATRMP6 = 0, it compensates for negative
offset. ATRMP5:0 are the magnitude of the trim with 000000 = no trim value and 111111 = highest trim
value.
Trimming the Offset on the Programmable Gain Amplifier
Setting the TRIM bit puts the programmable gain amplifier into a special configuration used for trimming the
offset, which is shown in Figure 30. This configuration enables the amplifier and puts it into open loop gain. By
selecting the reference voltages, VREFN and VREFP, one at a time, the offset can be calibrated using the A/D
converter. The calibration routine uses software to perform a successive approximation algorithm and is indicated
below. After the trim algorithm is complete, the trim values are stored in the AMPTRMN and AMPTRMP registers
and should remain, unchanged, until the algorithm is executed again. The trim values stored in AMPTRMN and
AMPTRMP values are lost if any type of reset is generated. Therefore, it's necessary to retrim after any type of
Reset. A method to minimize retrimming would be to store the initial trim values into the virtual EEPROM
memory in addition to AMPTRMN and AMPTRMP. Then, whenever necessary, the trim values could be retrieved
from virtual EEPROM, avoiding execution of the trim algorithm upon a Reset.
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