COP8AME9_14 Datasheet, PDF (53/102 Pages) Texas Instruments – COP8AME9 8-Bit CMOS Flash Microcontroller with 8k Memory, Dual Op Amps, Virtual EEPROM, Temperature Sensor, 10-Bit A/D and Brownout Reset

COP8AME9, COP8ANE9
www.ti.com
SNOS930F – MARCH 2001 – REVISED MARCH 2013
Note: The CKX pin is unavailable if Port L1 is used for the Low Speed Oscillator.
USART OPERATION
The USART has two modes of operation: asynchronous mode and synchronous mode.
Asynchronous Mode
This mode is selected by resetting the SSEL (in the ENUI register) bit to zero. The input frequency to the USART
is 16 times the baud rate.
The TSFT and TBUF registers double-buffer data for transmission. While TSFT is shifting out the current
character on the TDX pin, the TBUF register may be loaded by software with the next byte to be transmitted.
When TSFT finishes transmitting the current character the contents of TBUF are transferred to the TSFT register
and the Transmit Buffer Empty Flag (TBMT in the ENU register) is set. The TBMT flag is automatically reset by
the USART when software loads a new character into the TBUF register. There is also the XMTG bit which is set
to indicate that the USART is transmitting. This bit gets reset at the end of the last frame (end of last Stop bit).
TBUF is a read/write register.
The RSFT and RBUF registers double-buffer data being received. The USART receiver continually monitors the
signal on the RDX pin for a low level to detect the beginning of a Start bit. Upon sensing this low level, it waits for
half a bit time and samples again. If the RDX pin is still low, the receiver considers this to be a valid Start bit, and
the remaining bits in the character frame are each sampled three times around the center of the bit time. Serial
data input on the RDX pin is shifted into the RSFT register. Upon receiving the complete character, the contents
of the RSFT register are copied into the RBUF register and the Received Buffer Full Flag (RBFL) is set. RBFL is
automatically reset when software reads the character from the RBUF register. RBUF is a read only register.
There is also the RCVG bit which is set high when a framing error or break detect occurs and goes low once
RDX goes high.
Synchronous Mode
In this mode data is transferred synchronously with the clock. Data is transmitted on the rising edge and received
on the falling edge of the synchronous clock.
This mode is selected by setting SSEL bit in the ENUI register. The input frequency to the USART is the same
as the baud rate.
When an external clock input is selected at the CKX pin, data transmit and receive are performed synchronously
with this clock through TDX/RDX pins.
If data transmit and receive are selected with the CKX pin as clock output, the device generates the synchronous
clock output at the CKX pin. The internal baud rate generator is used to produce the synchronous clock. Data
transmit and receive are performed synchronously with this clock.
FRAMING FORMATS
The USART supports several serial framing formats (Figure 24). The format is selected using control bits in the
ENU, ENUR and ENUI registers.
The first format (1, 1a, 1b, 1c) for data transmission (CHL0 = 1, CHL1 = 0) consists of Start bit, seven Data bits
(excluding parity) and one or two Stop bits. In applications using parity, the parity bit is generated and verified by
hardware.
The second format (CHL0 = 0, CHL1 = 0) consists of one Start bit, eight Data bits (excluding parity) and one or
two Stop bits. Parity bit is generated and verified by hardware.
The third format for transmission (CHL0 = 0, CHL1 = 1) consists of one Start bit, nine Data bits and one or two
Stop bits. This format also supports the USART “ATTENTION” feature. When operating in this format, all eight
bits of TBUF and RBUF are used for data. The ninth data bit is transmitted and received using two bits in the
ENU and ENUR registers, called XBIT9 and RBIT9. RBIT9 is a read only bit. Parity is not generated or verified in
this mode.
The parity is enabled/disabled by PEN bit located in the ENU register. Parity is selected for 7- and 8-bit modes
only. If parity is enabled (PEN = 1), the parity selection is then performed by PSEL0 and PSEL1 bits located in
the ENU register.
Copyright © 2001–2013, Texas Instruments Incorporated
Submit Documentation Feedback
53
Product Folder Links: COP8AME9 COP8ANE9