COP8AME9_14 Datasheet, PDF (36/102 Pages) Texas Instruments – COP8AME9 8-Bit CMOS Flash Microcontroller with 8k Memory, Dual Op Amps, Virtual EEPROM, Temperature Sensor, 10-Bit A/D and Brownout Reset

COP8AME9, COP8ANE9
SNOS930F – MARCH 2001 – REVISED MARCH 2013
www.ti.com
Either or both of the timer underflow interrupts may be enabled. This gives the user the flexibility of interrupting
once per PWM period on either the rising or falling edge of the PWM output. Alternatively, the user may choose
to interrupt on both edges of the PWM output.
Figure 17. Timer in PWM Mode
If either T2 or T3 is used in High Speed PWM mode and an SBIT or RBIT instruction operates on any other bit of
the PORT L Data Register, the PWM output may appear to miss a toggle and thus be inverted. If the timer
causes the PWM output to toggle in the middle of an SBIT or RBIT operation on the PORTLD Register, the PWM
output may be set back to its state before the output toggle by the operation of the SBIT/RBIT. This can have the
effect of generating a shortened pulse (less than one instruction cycle in width) on the PWM output and inverting
the PWM duty cycle.
If the PWM Timer is used in low speed mode or if the PWM output toggle is synchronous with the end of the
instruction cycle, this problem is not seen. The following figure illustrates the PWM output when the failure is
seen.
The user should be aware of the state of Timers T2 and T3 before any SBIT or RBIT instructions are executed
which operate on the PORTLD register. If the PWM output is close to toggling, the user should delay the SBIT or
RBIT instruction.
The following program sequence works to delay the operation. The user may wish to experiment with other
sequences to see which best fits the application and to make sure that the time between the completion of the
tests and the modification of PORTLD is not too long. The sequence can easily be modified to work with Timer
T3.
LD B,#TMR2HI ;POINT B TO THE TIMER
LD A,[B-] ;GET THE VALUE IN THE TIMER
IFGT A,#0 ;IF NON ZERO
JP GOOD ;WE HAVE TIME
WAIT: IFBIT 6,[B] ;TEST BIT 6 OF THE TIMER
JP GOOD ;TIME TO GET IT DONE SAFELY
JP WAIT ;WAIT A WHILE
GOOD: SBIT 2,PORTLD ;GO AHEAD AND SET THE BIT
The above program uses specific bits of the port for explanation purposes only.
The above program uses the SBIT instruction by way of example. The RBIT instruction will have the same effect.
The above sequence will not work properly for PWM times shorter than 64 CPU Clock cycles.
The choice of TMR2LO bit 6 works, but may introduce delay at the wrong time in some applications, particularly
if bit 7 is a one. The above example shows the workaround if only one timer (T2 or T3) is used in high speed
PWM mode. If both Timers T2 and T3 are used in high speed PWM mode, the program becomes significantly
more complicated, since the execution of the SBIT or RBIT instruction must be delayed until the PWM output of
neither T2 nor T3 is likely to change during the execution of the instruction.
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