COP8AME9_14 Datasheet, PDF (44/102 Pages) Texas Instruments – COP8AME9 8-Bit CMOS Flash Microcontroller with 8k Memory, Dual Op Amps, Virtual EEPROM, Temperature Sensor, 10-Bit A/D and Brownout Reset

COP8AME9, COP8ANE9
SNOS930F – MARCH 2001 – REVISED MARCH 2013
www.ti.com
The device is placed in the IDLE mode under software control by setting the IDLE bit (bit 6 of the Port G data
register).
The IDLE Timer window is selectable from one of five values, 4k, 8k, 16k, 32k or 64k instruction cycles. Selection
of this value is made through the ITMR register.
The IDLE mode uses the on-chip IDLE Timer (Timer T0) to keep track of elapsed time in the IDLE state. The
IDLE Timer runs continuously at the instruction clock rate, whether or not the device is in the IDLE mode. Each
time the bit of the timer associated with the selected window toggles, the T0PND bit is set, an interrupt is
generated (if enabled), and the device exits the IDLE mode if in that mode. If the IDLE Timer interrupt is enabled,
the interrupt is serviced before execution of the main program resumes. (However, the instruction which was
started as the part entered the IDLE mode is completed before the interrupt is serviced. This instruction should
be a NOP which should follow the enter IDLE instruction.) The user must reset the IDLE Timer pending flag
(T0PND) before entering the IDLE mode.
As with the HALT mode, this device can also be returned to normal operation with a RESET, or with a Multi-Input
Wake-up input. Upon reset the ITMR register is cleared and the ITMR register selects the 4,096 instruction cycle
tap of the IDLE Timer.
The IDLE Timer cannot be started or stopped under software control, and it is not memory mapped, so it cannot
be read or written by the software. Its state upon Reset is unknown. Therefore, if the device is put into the IDLE
mode at an arbitrary time, it will stay in the IDLE mode for somewhere between 1 and the selected number of
instruction cycles.
In order to precisely time the duration of the IDLE state, entry into the IDLE mode must be synchronized to the
state of the IDLE Timer. The best way to do this is to use the IDLE Timer interrupt, which occurs on every
underflow of the bit of the IDLE Timer which is associated with the selected window. Another method is to poll
the state of the IDLE Timer pending bit T0PND, which is set on the same occurrence. The Idle Timer interrupt is
enabled by setting bit T0EN in the ICNTRL register.
Any time the IDLE Timer window length is changed there is the possibility of generating a spurious IDLE Timer
interrupt by setting the T0PND bit. The user is advised to disable IDLE Timer interrupts prior to changing the
value of the ITSEL bits of the ITMR Register and then clear the TOPND bit before attempting to synchronize
operation to the IDLE Timer.
Note: As with the HALT mode, it is necessary to program two NOP's to allow clock resynchronization upon
return from the IDLE mode. The NOP's are placed either at the beginning of the IDLE Timer interrupt routine or
immediately following the “enter IDLE mode” instruction.
For more information on the IDLE Timer and its associated interrupt, see the description in section TIMER T0
(IDLE TIMER).
DUAL CLOCK MODE OPERATION
This mode of operation allows for high speed operation of the Core clock and low speed operation of the Idle
Timer. This mode can be entered from either the High Speed mode or the Low Speed mode.
To enter from the High Speed mode, the following sequence must be followed:
1. Software sets the LSON bit to 1.
2. Software waits until the low speed oscillator has stabilized. See Table 5.
3. Software sets the DCEN bit to 1.
To enter from the Low Speed mode, the following sequence must be followed:
1. Software sets the HSON bit to 1.
2. Software waits until the high speed oscillator has stabilized. See Table 5, Startup Times.
3. Software clears the CCKSEL bit to 0.
Dual Clock HALT Mode
The fully static architecture of this device allows the state of the microcontroller to be frozen. This is
accomplished by stopping the high speed clock of the device during the HALT mode. The processor can be
forced to exit the HALT mode and resume normal operation at any time. The low speed clock remains on during
HALT in the Dual Clock mode.
44
Submit Documentation Feedback
Copyright © 2001–2013, Texas Instruments Incorporated
Product Folder Links: COP8AME9 COP8ANE9