COP8AME9_14 Datasheet, PDF (45/102 Pages) Texas Instruments – COP8AME9 8-Bit CMOS Flash Microcontroller with 8k Memory, Dual Op Amps, Virtual EEPROM, Temperature Sensor, 10-Bit A/D and Brownout Reset

COP8AME9, COP8ANE9
www.ti.com
SNOS930F – MARCH 2001 – REVISED MARCH 2013
During normal operation, the actual power consumption depends heavily on the clock speed and operating
voltage used in an application and is shown in the Electrical Specifications. In the HALT mode, the device only
draws a small leakage current, plus current for the BOR feature, plus the 32 kHz oscillator current, plus any
current necessary for driving the outputs. Since total power consumption is affected by the amount of current
required to drive the outputs, all I/Os should be configured to draw minimal current prior to entering the HALT
mode, if possible.
Entering The Dual Clock Halt Mode
The device enters the HALT mode under software control when the Port G data register bit 7 is set to 1. All
processor action stops in the middle of the next instruction cycle, and power consumption is reduced to a very
low level. In order to expedite exit from HALT, the low speed oscillator is left running when the device is Halted in
the Dual Clock mode. However, the Idle Timer will not be clocked.
Exiting The Dual Clock Halt Mode
When the HALT mode is entered by setting bit 7 of the Port G data register, there is a choice of methods for
exiting the HALT mode: a chip Reset using the RESET pin or a Multi-Input Wake-up. The Reset method and
Multi-Input Wake-up method can be used with any clock option.
HALT Exit Using Reset
A device Reset, which is invoked by a low-level signal on the RESET input pin, takes the device out of the Dual
Clock mode and puts it into the High Speed mode.
HALT Exit Using Multi-Input Wake-up
The device can be brought out of the HALT mode by a transition received on one of the available Wake-up pins.
The pins used and the types of transitions sensed on the Multi-input pins are software programmable. For
information on programming and using the Multi-Input Wake-up feature, refer to MULTI-INPUT WAKE-UP.
A start-up delay is required between the device wake-up and the execution of program instructions. The start-up
delay is mandatory, and is implemented whether or not the CLKDLY bit is set. This is because all crystal
oscillators and resonators require some time to reach a stable frequency and full operating amplitude.
If the start-up delay is used, the IDLE Timer (Timer T0) provides a fixed delay from the time the clock is enabled
to the time the program execution begins. Upon exit from the HALT mode, the IDLE Timer is enabled with a
starting value of 256 and is decremented with each instruction cycle using the high speed clock. (The instruction
clock runs at one-fifth the frequency of the high speed oscillatory.) An internal Schmitt trigger connected to the
on-chip CKI inverter ensures that the IDLE Timer is clocked only when the high speed oscillator has a large
enough amplitude. (The Schmitt trigger is not part of the oscillator closed loop.) When the IDLE Timer
underflows, the clock signals are enabled on the chip, allowing program execution to proceed. Thus, the delay is
equal to 256 instruction cycles. After exiting HALT, the Idle Timer will return to being clocked by the low speed
clock.
Note: To ensure accurate operation upon start-up of the device using Multi-input Wake-up, the instruction in the
application program used for entering the HALT mode should be followed by two consecutive NOP (no-
operation) instructions.
Options
This device has two options associated with the HALT mode. The first option enables the HALT mode feature,
while the second option disables HALT mode operation. Selecting the disable HALT mode option will cause the
microcontroller to ignore any attempts to HALT the device under software control. See OPTION REGISTER for
more details on this option bit.
Dual Clock Idle Mode
In the IDLE mode, program execution stops and power consumption is reduced to a very low level as with the
HALT mode. However, both oscillators, IDLE Timer (Timer T0), T2 timer (T2HS = 1, T2IDLE = 1), and Clock
Monitor continue to operate, allowing real time to be maintained. The Idle Timer is clocked by the low speed
clock. The device remains idle for a selected amount of time up to 1 second, and then automatically exits the
IDLE mode and returns to normal program execution using the high speed clock.
Copyright © 2001–2013, Texas Instruments Incorporated
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