COP8AME9_14 Datasheet, PDF (83/102 Pages) Texas Instruments – COP8AME9 8-Bit CMOS Flash Microcontroller with 8k Memory, Dual Op Amps, Virtual EEPROM, Temperature Sensor, 10-Bit A/D and Brownout Reset

COP8AME9, COP8ANE9
www.ti.com
SNOS930F – MARCH 2001 – REVISED MARCH 2013
Address
S/ADD REG
xxE7
xxE8
xxE9
xxEA
xxEB
xxEC
xxED
xxEE
xxEF
xxF0 to FB
xxFC
xxFD
xxFE
xxFF
0100 to 017F
0200 to 027F
0300 to 037F
Contents
Timer T1 Autoload Register T1RB Upper Byte
ICNTRL Register
MICROWIRE/PLUS Shift Register
Timer T1 Lower Byte
Timer T1 Upper Byte
Timer T1 Autoload Register T1RA Lower Byte
Timer T1 Autoload Register T1RA Upper Byte
CNTRL Control Register
PSW Register
On-Chip RAM Mapped as Registers
X Register
SP Register
B Register
S Register
On-Chip 128 RAM Bytes
On-Chip 128 RAM Bytes
On-Chip 128 RAM Bytes
NOTE
Reading memory locations 0070H–007FH (Segment 0) will return all ones. Reading
unused memory locations 0080H–0093H (Segment 0) will return undefined data. Reading
memory locations from other Segments (i.e., Segment 4, Segment 5, … etc.) will return
undefined data.
Instruction Set
INTRODUCTION
This section defines the instruction set of the COP8 Family members. It contains information about the instruction
set features, addressing modes and types.
INSTRUCTION FEATURES
The strength of the instruction set is based on the following features:
• Mostly single-byte opcode instructions minimize program size.
• One instruction cycle for the majority of single-byte instructions to minimize program execution time.
• Many single-byte, multiple function instructions such as DRSZ.
• Three memory mapped pointers: two for register indirect addressing, and one for the software stack.
• Sixteen memory mapped registers that allow an optimized implementation of certain instructions.
• Ability to set, reset, and test any individual bit in data memory address space, including the memory-mapped
I/O ports and registers.
• Register-Indirect LOAD and EXCHANGE instructions with optional automatic post-incrementing or
decrementing of the register pointer. This allows for greater efficiency (both in cycle time and program code)
in loading, walking across and processing fields in data memory.
• Unique instructions to optimize program size and throughput efficiency. Some of these instructions are:
DRSZ, IFBNE, DCOR, RETSK, VIS and RRC.
Copyright © 2001–2013, Texas Instruments Incorporated
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