COP8AME9_14 Datasheet, PDF (38/102 Pages) Texas Instruments – COP8AME9 8-Bit CMOS Flash Microcontroller with 8k Memory, Dual Op Amps, Virtual EEPROM, Temperature Sensor, 10-Bit A/D and Brownout Reset

COP8AME9, COP8ANE9
SNOS930F – MARCH 2001 – REVISED MARCH 2013
www.ti.com
Underflows from the timer can also be programmed to generate interrupts. Underflows are latched into the timer
TxC0 pending flag (the TxC0 control bit serves as the timer underflow interrupt pending flag in the Input Capture
mode). Consequently, the TxC0 control bit should be reset when entering the Input Capture mode. The timer
underflow interrupt is enabled with the TxENA control flag. When a TxA interrupt occurs in the Input Capture
mode, the user must check both the TxPNDA and TxC0 pending flags in order to determine whether a TxA input
capture or a timer underflow (or both) caused the interrupt.
Figure 19 shows a block diagram of the timer T1 in Input Capture mode. T2 and T3 are identical to T1.
Figure 19. Timer in Input Capture Mode
TIMER CONTROL FLAGS
The control bits and their functions are summarized below.
TxC3 Timer mode control
TxC2 Timer mode control
TxC1 Timer mode control
TxC0 Timer Start/Stop control in Modes 1 and 2 (Processor Independent PWM and External Event Counter),
where 1 = Start, 0 = Stop
Timer Underflow Interrupt Pending Flag in Mode 3 (Input Capture)
TxPNDA Timer Interrupt Pending Flag
TxENA Timer Interrupt Enable Flag
1 = Timer Interrupt Enabled
0 = Timer Interrupt Disabled
TxPNDB Timer Interrupt Pending Flag
TxENB Timer Interrupt Enable Flag
1 = Timer Interrupt Enabled
0 = Timer Interrupt Disabled
The timer mode control bits (TxC3, TxC2 and TxC1) are detailed in Table 17, Timer Operating Modes.
When the high speed timers are counting in high speed mode, directly altering the contents of the timer upper or
lower registers, the PWM outputs or the reload registers is not recommended. Bit operations can be particularly
problematic. Since any of these six registers or the PWM outputs can change as many as ten times in a single
instruction cycle, performing an SBIT or RBIT operation with the timer running can produce unpredictable results.
The recommended procedure is to stop the timer, perform any changes to the timer, the PWM outputs or reload
register values, and then re-start the timer. This warning does not apply to the timer control register. Any type of
read/write operation, including SBIT and RBIT may be performed on this register in any operating mode.
38
Submit Documentation Feedback
Copyright © 2001–2013, Texas Instruments Incorporated
Product Folder Links: COP8AME9 COP8ANE9