COP8AME9_14 Datasheet, PDF (29/102 Pages) Texas Instruments – COP8AME9 8-Bit CMOS Flash Microcontroller with 8k Memory, Dual Op Amps, Virtual EEPROM, Temperature Sensor, 10-Bit A/D and Brownout Reset

COP8AME9, COP8ANE9
www.ti.com
SNOS930F – MARCH 2001 – REVISED MARCH 2013
Table 11. KEY Register Write Format
KEY When Writing
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
1
0
0
1
1
0
Bits 7–2: Key value that must be written to set the KEY bit.
Bits 1–0: Don't care.
Bit 1
X
Bit 0
X
FORCED EXECUTION FROM BOOT ROM
When the user is developing a customized ISP routine, code lockups due to software errors may be
encountered. The normal, and preferred, method to recover from these conditions is to reprogram the device with
the corrected code by either an external parallel programmer or the emulation tools. As a last resort, when this
equipment is not available, there is a hardware method to get out of these lockups and force execution from the
Boot ROM MICROWIRE/PLUS routine. The customer will then be able to erase the Flash Memory code and start
over.
The method to force this condition is to drive the G6 pin to high voltage (2 x V_CC) and activate Reset. The high
voltage condition on G6 must not be applied before V_CC is valid and stable, and must be held for at least 3
instruction cycles longer than Reset is active. This special condition will bypass checking the state of the Flex bit
in the Option Register and will start execution from location 0000 in the Boot ROM. In this state, the user can
input the appropriate commands, using MICROWIRE/PLUS, to erase the flash program memory and reprogram
it. If the device is subsequently reset before the Flex bit has been erased by specific Page Erase or Mass Erase
ISP commands, execution will start from location 0000 in the Flash program memory. The high voltage (2 x V_CC)
on G6 will not erase either the Flex or the Security bit in the Option Register. The Security bit, if set, can only be
erased by a Mass Erase of the entire contents of the Flash Memory unless under the control of User ISP
routines in the Application Program.
While the G6 pin is at high voltage, the Load Clock will be output onto G5, which will look like an SK clock to the
MICROWIRE/PLUS routine executing in slave mode. However, when G6 is at high voltage, the G6 input will also
look like a logic 1. The MICROWIRE/PLUS routine in Boot ROM monitors the G6 input, waits for it to go low,
debounces it, and then enables the ISP routine. CAUTION: The Load clock on G5 could be in conflict with the
user's external SK. It is up to the user to resolve this conflict, as this condition is considered a minor issue that's
only encountered during software development. The user should also be cautious of the high voltage
applied to the G6 pin. This high voltage could damage other circuitry connected to the G6 pin (e.g. the
parallel port of a PC). The user may wish to disconnect other circuitry while G6 is connected to the high
voltage.
V_CC must be valid and stable before high voltage is applied to G6.
The correct sequence to be used to force execution from Boot ROM is :
1. Disconnect G6 from the source of data for MICROWIRE/PLUS ISP.
2. Apply V_CC to the device.
3. Pull RESET Low.
4. After V_CC is valid and stable, connect a voltage between 2 x V_CC and V_CC+7V to the G6 pin. Ensure that the
rise time of the high voltage on G6 is slower than the minimum in the Electrical Specifications.Figure 15
shows a possible circuit dliagram for implementing the 2 x V_CC. Be aware of the typical input current on the
G6 pin when the high voltage is applied. The resistor used in the RC network, and the high voltage used,
should be chosen to keep the high voltage at the G6 pin between 2 x V_CC and V_CC+7V.
5. Pull RESET High.
6. After a delay of at least three instruction cycles, remove the high voltage from G6.
Figure 15. Circuit Diagram for Implementing the 2 x V_CC
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