COP8AME9_14 Datasheet, PDF (31/102 Pages) Texas Instruments – COP8AME9 8-Bit CMOS Flash Microcontroller with 8k Memory, Dual Op Amps, Virtual EEPROM, Temperature Sensor, 10-Bit A/D and Brownout Reset

COP8AME9, COP8ANE9
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SNOS930F – MARCH 2001 – REVISED MARCH 2013
USER ISP AND VIRTUAL E²
The following commands will support transferring blocks of data from RAM to flash program memory, and vice-
versa. The user is expected to enforce application security in this case.
• Erase the entire flash program memory (mass erase). NOTE: Execution of this command will force the device
into the MICROWIRE/PLUS ISP mode.
• Erase a page of flash memory at a specified address.
• Read a byte from a specified address.
• Write a byte to a specified address.
• Copy a block of data from RAM into flash program memory.
• Copy a block of data from program flash memory to RAM.
The following table lists the User ISP/Virtual E² commands, required parameters and return data, if applicable.
The command entry point is used as an argument to the JSRB instruction. Table 14 lists the Ram locations and
Peripheral Registers, used for User ISP and Virtual E², and their expected contents. Please refer to the COP8
FLASH ISP User Manual for additional information and programming examples on the use of User ISP and
Virtual E².
Command/
Label
cpgerase
Function
Page Erase
cmserase
creadbf
Mass Erase
Read Byte
cblockr
Block Read
cwritebf
Write Byte
cblockw
Block Write
exit
EXIT
Table 13. User ISP/Virtual E² Entry Points
Command
Entry Point
0x17
0x1A
0x11
0x26
0x14
0x23
0x62
Parameters
Return Data
Register ISPADHI is loaded by the user with N/A (A page of memory beginning at
the high byte of the address.
ISPADHI, ISPADLO will be erased)
Register ISPADLO is loaded by the user
with the low byte of the address.
Accumulator A contains the confirmation
key 0x55.
N/A (The entire Flash Memory will be
erased)
Register ISPADHI is loaded by the user with Data Byte in Register ISPRD.
the high byte of the address.
Register ISPADLO is loaded by the user
with the low byte of the address.
Register ISPADHI is loaded by the user with n Data Bytes, Data will be returned
the high byte of the address.
beginning at a location pointed to by the
Register ISPADLO is loaded by the user
RAM address in X.
with the low byte of the address.
X pointer contains the beginning RAM
address where the result(s) will be returned.
Register BYTECOUNTLO contains the
number of n bytes to read (0 ≤ n ≤ 255). It is
up to the user to setup the segment register.
Register ISPADHI is loaded by the user with N/A
the high byte of the address.
Register ISPADLO is loaded by the user
with the low byte of the address.
Register ISPWR contains the Data Byte to
be written.
Register ISPADHI is loaded by the user with N/A
the high byte of the address.
Register ISPADLO is loaded by the user
with the low byte of the address.
Register BYTECOUNTLO contains the
number of n bytes to write (0 ≤ n ≤ 16).
The combination of the BYTECOUNTLO
and the ISPADLO registers must be set
such that the operation will not cross a 64
byte boundary.
X pointer contains the beginning RAM
address of the data to be written.
It is up to the user to setup the segment
register.
N/A
N/A (Device will Reset)
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