COP8AME9_14 Datasheet, PDF (42/102 Pages) Texas Instruments – COP8AME9 8-Bit CMOS Flash Microcontroller with 8k Memory, Dual Op Amps, Virtual EEPROM, Temperature Sensor, 10-Bit A/D and Brownout Reset

COP8AME9, COP8ANE9
SNOS930F – MARCH 2001 – REVISED MARCH 2013
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RSVD: This bit is reserved and must be 0.
ITSEL2–0: These are bits used to control the Idle Timer. See TIMER T0 (IDLE TIMER) for the description of
these bits.
Table 20 lists the valid contents of the four most significant bits of the ITMR Register. States are presented in the
only valid sequence. Any other value is illegal and will result in an unrecoverable loss of a clock to the CPU core.
To prevent this condition, the device will automatically reset if any illegal value is detected.
LSON
0
1
1
1
1
Table 20. Valid Contents of Dual Clock Control Bits
HSON
1
1
1
1
0
DCEN
0
0
1
1
1
CCKSEL
0
0
0
1
1
Mode
High Speed
High Speed/Dual Clock Transition
Dual Clock
Dual Clock/Low Speed Transition
Low Speed
OSCILLATOR STABILIZATION
Both the high speed oscillator and low speed oscillator have a startup delay associated with them. When
switching between the modes, the software must ensure that the appropriate oscillator is started up and
stabilized before switching to the new mode. See Table 5, Startup Times for startup times for both oscillators.
HIGH SPEED MODE OPERATION
This mode of operation allows high speed operation for both the main Core clock and also for the IDLE Timer.
This is the default mode of the device and will always be entered upon any of the Reset conditions described in
the Reset section. It can also be entered from Dual Clock mode. It cannot be directly entered from the Low
Speed mode without passing through the Dual Clock mode first.
To enter from the Dual Clock mode, the following sequence must be followed using two separate instructions:
1. Software clears DCEN to 0.
2. Software clears LSON to 0.
High Speed Halt Mode
The fully static architecture of this device allows the state of the microcontroller to be frozen. This is
accomplished by stopping the internal clock of the device during the HALT mode. The controller also stops the
CKI pin from oscillating during the HALT mode. The processor can be forced to exit the HALT mode and resume
normal operation at any time.
During normal operation, the actual power consumption depends heavily on the clock speed and operating
voltage used in an application and is shown in the Electrical Specifications. In the HALT mode, the device only
draws a small leakage current, plus current for the BOR feature, plus any current necessary for driving the
outputs. Since total power consumption is affected by the amount of current required to drive the outputs, all I/Os
should be configured to draw minimal current prior to entering the HALT mode, if possible. In order to reduce
power consumption even further, the power supply (V_CC) can be reduced to a very low level during the HALT
mode, just high enough to ensure retention of data stored in RAM. The allowed lower voltage level (V_R) is
specified in the Electrical Specs section.
Entering The High Speed Halt Mode
The device enters the HALT mode under software control when the Port G data register bit 7 is set to 1. All
processor action stops in the middle of the next instruction cycle, and power consumption is reduced to a very
low level.
Exiting The High Speed Halt Mode
There is a choice of methods for exiting the HALT mode: a chip Reset using the RESET pin or a Multi-Input
Wake-up.
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