COP8AME9_14 Datasheet, PDF (33/102 Pages) Texas Instruments – COP8AME9 8-Bit CMOS Flash Microcontroller with 8k Memory, Dual Op Amps, Virtual EEPROM, Temperature Sensor, 10-Bit A/D and Brownout Reset

COP8AME9, COP8ANE9
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Erase Time
1 ms
2 ms
3 ms
4 ms
5 ms
6 ms
7 ms
8 ms
SNOS930F – MARCH 2001 – REVISED MARCH 2013
−40°C
60k
60k
60k
60k
70k
80k
90k
100k
Table 15. Typical Flash Memory Endurance
Low End of Operating Temp Range
−20°C
0°C
60k
60k
60k
60k
60k
60k
60k
100k
70k
100k
80k
100k
90k
100k
100k
100k
25°C
100k
100k
100k
100k
100k
100k
100k
100k
>25°C
100k
100k
100k
100k
100k
100k
100k
100k
Timers
The device contains a very versatile set of timers (T0, T1, T2 and T3). Timers T1, T2 and T3 and associated
autoreload/capture registers power up containing random data.
TIMER T0 (IDLE TIMER)
The device supports applications that require maintaining real time and low power with the IDLE mode. This
IDLE mode support is furnished by the IDLE Timer T0, which is a 16-bit timer. The user cannot read or write to
the IDLE Timer T0, which is a count down timer.
As described in Power Saving Features, the clock to the IDLE Timer depends on which mode the device is in. If
the device is in High Speed mode, the clock to the IDLE Timer is the instruction cycle clock (one-fifth of the CKI
frequency). If the device is in Dual Clock mode or Low Speed mode, the clock to the IDLE Timer is the 32 kHz
clock. For the remainder of this section, the term “selected clock” will refer to the clock selected by the Power
Save mode of the device. During Dual Clock and Low Speed modes, the divide by 10 that creates the instruction
cycle clock is disabled, to minimize power consumption.
In addition to its time base function, the Timer T0 supports the following functions:
• Exit out of the Idle Mode (See Idle Mode description)
• WATCHDOG logic (See WATCHDOG description)
• Start up delay out of the HALT mode
• Start up delay from BOR
Figure 16 is a functional block diagram showing the structure of the IDLE Timer and its associated interrupt logic.
Bits 11 through 15 of the ITMR register can be selected for triggering the IDLE Timer interrupt. Each time the
selected bit underflows (every 4k, 8k, 16k, 32k or 64k selected clocks), the IDLE Timer interrupt pending bit
T0PND is set, thus generating an interrupt (if enabled), and bit 6 of the Port G data register is reset, thus causing
an exit from the IDLE mode if the device is in that mode.
In order for an interrupt to be generated, the IDLE Timer interrupt enable bit T0EN must be set, and the GIE
(Global Interrupt Enable) bit must also be set. The T0PND flag and T0EN bit are bits 5 and 4 of the ICNTRL
register, respectively. The interrupt can be used for any purpose. Typically, it is used to perform a task upon exit
from the IDLE mode. For more information on the IDLE mode, refer to section Power Saving Features.
The Idle Timer period is selected by bits 0–2 of the ITMR register Bit 3 of the ITMR Register is reserved and
should not be used as a software flag. Bits 4 through 7 of the ITMR Register are used by the dual clock and are
described in Power Saving Features.
Copyright © 2001–2013, Texas Instruments Incorporated
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