COP8AME9_14 Datasheet, PDF (71/102 Pages) Texas Instruments – COP8AME9 8-Bit CMOS Flash Microcontroller with 8k Memory, Dual Op Amps, Virtual EEPROM, Temperature Sensor, 10-Bit A/D and Brownout Reset

COP8AME9, COP8ANE9
www.ti.com
SNOS930F – MARCH 2001 – REVISED MARCH 2013
The vector table may be as long as 32 bytes (maximum of 16 vectors) and resides at the top of the 256-byte
block containing the VIS instruction. However, if the VIS instruction is at the very top of a 256-byte block (such as
at 00FF Hex), the vector table resides at the top of the next 256-byte block. Thus, if the VIS instruction is located
somewhere between 00FF and 01DF Hex (the usual case), the vector table is located between addresses 01E0
and 01FF Hex. If the VIS instruction is located between 01FF and 02DF Hex, then the vector table is located
between addresses 02E0 and 02FF Hex, and so on.
Each vector is 15 bits long and points to the beginning of a specific interrupt service routine somewhere in the
32-kbyte memory space. Each vector occupies two bytes of the vector table, with the higher-order byte at the
lower address. The vectors are arranged in order of interrupt priority. The vector of the maskable interrupt with
the lowest rank is located to 0yE0 (higher-order byte) and 0yE1 (lower-order byte). The next priority interrupt is
located at 0yE2 and 0yE3, and so forth in increasing rank. The Software Trap has the highest rand and its vector
is always located at 0yFE and 0yFF. The number of interrupts which can become active defines the size of the
table.
Table 35 shows the types of interrupts, the interrupt arbitration ranking, and the locations of the corresponding
vectors in the vector table.
The vector table should be filled by the user with the memory locations of the specific interrupt service routines.
For example, if the Software Trap routine is located at 0310 Hex, then the vector location 0yFE and -0yFF should
contain the data 03 and 10 Hex, respectively. When a Software Trap interrupt occurs and the VIS instruction is
executed, the program jumps to the address specified in the vector table.
The interrupt sources in the vector table are listed in order of rank, from highest to lowest priority. If two or more
enabled and pending interrupts are detected at the same time, the one with the highest priority is serviced first.
Upon return from the interrupt service routine, the next highest-level pending interrupt is serviced.
If the VIS instruction is executed, but no interrupts are enabled and pending, the lowest-priority interrupt vector is
used, and a jump is made to the corresponding address in the vector table. This is an unusual occurrence and
may be the result of an error. It can legitimately result from a change in the enable bits or pending flags prior to
the execution of the VIS instruction, such as executing a single cycle instruction which clears an enable flag at
the same time that the pending flag is set. It can also result, however, from inadvertent execution of the VIS
command outside of the context of an interrupt.
The default VIS interrupt vector can be useful for applications in which time critical interrupts can occur during
the servicing of another interrupt. Rather than restoring the program context (A, B, X, etc.) and executing the
RETI instruction, an interrupt service routine can be terminated by returning to the VIS instruction. In this case,
interrupts will be serviced in turn until no further interrupts are pending and the default VIS routine is started.
After testing the GIE bit to ensure that execution is not erroneous, the routine should restore the program context
and execute the RETI to return to the interrupted program.
This technique can save up to fifty instruction cycles (t_C), or more, (25 µs at 10 MHz oscillator) of latency for
pending interrupts with a penalty of fewer than ten instruction cycles if no further interrupts are pending.
To ensure reliable operation, the user should always use the VIS instruction to determine the source of an
interrupt. Although it is possible to poll the pending bits to detect the source of an interrupt, this practice is not
recommended. The use of polling allows the standard arbitration ranking to be altered, but the reliability of the
interrupt system is compromised. The polling routine must individually test the enable and pending bits of each
maskable interrupt. If a Software Trap interrupt should occur, it will be serviced last, even though it should have
the highest priority. Under certain conditions, a Software Trap could be triggered but not serviced, resulting in an
inadvertent “locking out” of all maskable interrupts by the Software Trap pending flag. Problems such as this can
be avoided by using VIS instruction.
Arbitration Ranking
(1) Highest
(2)
(3)
(4)
Software
Reserved for NMI
External
Timer T0
Table 35. Interrupt Vector Table
Source Description
INTR Instruction
G0
Underflow
Vector Address ⁽¹⁾
(Hi-Low Byte)
0yFE–0yFF
0yFC–0yFD
0yFA–0yFB
0yF8–0yF9
(1) y is a variable which represents the VIS block. VIS and the vector table must be located in the same 256-byte block except if VIS is
located at the last address of a block. In this case, the table must be in the next block.
Copyright © 2001–2013, Texas Instruments Incorporated
Submit Documentation Feedback
71
Product Folder Links: COP8AME9 COP8ANE9