COP8AME9_14 Datasheet, PDF (67/102 Pages) Texas Instruments – COP8AME9 8-Bit CMOS Flash Microcontroller with 8k Memory, Dual Op Amps, Virtual EEPROM, Temperature Sensor, 10-Bit A/D and Brownout Reset

COP8AME9, COP8ANE9
www.ti.com
SNOS930F – MARCH 2001 – REVISED MARCH 2013
The A/D Converter takes 15 A/D clock cycles to complete a conversion. Thus the minimum A/D conversion time
is 12 µs when a prescaler of 16 has been selected with MCLK = 20 MHz. The 15 A/D clock cycles needed for
conversion consist of 3 cycles for sampling, 1 cycle for auto-zeroing the comparator, 10 cycles for converting, 1
cycle for loading the result into the result registers and for stopping and re-initializing. The ADBSY flag provides
an A/D clock inhibit function, which saves power by powering down the A/D when it is not in use.
NOTE
The A/D Converter is also powered down when the device is in either the HALT or IDLE
modes. If the A/D is running when the device enters the HALT or IDLE modes, the A/D
powers down and then restarts the conversion from the beginning with a corrupted
sampled voltage (and thus an invalid result) when the device comes out of the HALT or
IDLE modes.
NOTE
If a Breakpoint is issued during an A/D conversion, the conversion will be completed.
ANALOG INPUT AND SOURCE RESISTANCE CONSIDERATIONS
Figure 31 shows the A/D pin model in single ended mode. The differential mode has a similar A/D pin model.
The leads to the analog inputs should be kept as short as possible. Both noise and digital clock coupling to an
A/D input can cause conversion errors. The clock lead should be kept away from the analog input line to reduce
coupling.
Source impedances greater than 3 kΩ on the analog input lines will adversely affect the internal RC charging
time during input sampling. As shown in Figure 31, the analog switch to the Sample & Hold capacitor is closed
only during the 3 A/D cycle sample time. Large source impedances on the analog inputs may result in the
Sample & Hold capacitor not being charged to the correct voltage levels, causing scale errors.
If large source resistance is necessary, the recommended solution is to slow down the A/D clock speed in
proportion to the source resistance. The A/D Converter may be operated at the maximum speed for R_S less than
3 kΩ. For R_S greater than 3 kΩ, A/D clock speed needs to be reduced. For example, with R_S = 6 kΩ, the A/D
Converter may be operated at half the maximum speed. A/D Converter clock speed may be slowed down by
either increasing the A/D prescaler divide-by or decreasing the CKI clock frequency. The A/D minimum clock
speed is 64 kHz.
*The analog switch is closed only during the sample time.
Figure 31. A/D Pin Model (Single Ended Mode)
Temperature Sensor
GENERAL DESCRIPTION
The Temperature Sensor on this device operates over a −40°C to +125°C temperature range and produces an
output voltage proportional to the device temperature. The transfer function is approximately linear. Refer to the
A/D Converter section to see how the Temperature Sensor is integrated with the Programmable Gain Amplifier
and A/D Converter.
The equation for V_OUT vs. temperature is:
V_OUT = [(−8.0 mV/°C) X T] + 1.65V
(3)
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