COP8AME9_14 Datasheet, PDF (72/102 Pages) Texas Instruments – COP8AME9 8-Bit CMOS Flash Microcontroller with 8k Memory, Dual Op Amps, Virtual EEPROM, Temperature Sensor, 10-Bit A/D and Brownout Reset

COP8AME9, COP8ANE9
SNOS930F – MARCH 2001 – REVISED MARCH 2013
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Arbitration Ranking
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16) Lowest
Table 35. Interrupt Vector Table (continued)
Source Description
Vector Address ⁽¹⁾
(Hi-Low Byte)
Timer T1
T1A/Underflow
0yF6–0yF7
Timer T1
T1B
0yF4–0yF5
MICROWIRE/PLUS
BUSY Low
0yF2–0yF3
Reserved
0yF0–0yF1
USART
Receive
0yEE–0yEF
USART
Transmit
0yEC–0yED
Timer T2
T2A/Underflow
0yEA–0yEB
Timer T2
T2B
0yE8–0yE9
Timer T3
T2A/Underflow
0yE6–0yE7
Timer T3
T3B
0yE4–0yE5
Port L/Wakeup
Port L Edge
0yE2–0yE3
Default VIS
Reserved
0yE0–0yE1
VIS Execution
When the VIS instruction is executed it activates the arbitration logic. The arbitration logic generates an even
number between E0 and FE (E0, E2, E4, E6 etc....) depending on which active interrupt has the highest
arbitration ranking at the time of the 1st cycle of VIS is executed. For example, if the software trap interrupt is
active, FE is generated. If the external interrupt is active and the software trap interrupt is not, then FA is
generated and so forth. If no active interrupt is pending, than E0 is generated. This number replaces the lower
byte of the PC. The upper byte of the PC remains unchanged. The new PC is therefore pointing to the vector of
the active interrupt with the highest arbitration ranking. This vector is read from program memory and placed into
the PC which is now pointed to the 1st instruction of the service routine of the active interrupt with the highest
arbitration ranking.
Figure 34 illustrates the different steps performed by the VIS instruction. Figure 35 shows a flowchart for the VIS
instruction.
The non-maskable interrupt pending flag is cleared by the RPND (Reset Non-Maskable Pending Bit) instruction
(under certain conditions) and upon RESET.
Figure 34. VIS Operation
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