COP8AME9_14 Datasheet, PDF (35/102 Pages) Texas Instruments – COP8AME9 8-Bit CMOS Flash Microcontroller with 8k Memory, Dual Op Amps, Virtual EEPROM, Temperature Sensor, 10-Bit A/D and Brownout Reset

COP8AME9, COP8ANE9
www.ti.com
SNOS930F – MARCH 2001 – REVISED MARCH 2013
TIMER T1, TIMER T2, AND TIMER T3
The device has a set of three powerful timer/counter blocks, T1, T2, and T3. Since T1, T2 and T3 are identical,
except for the high speed operation of T2 and T3, all comments are equally applicable to any of the three timer
blocks which will be referred to as Tx. Differences between the timers will be specifically noted.
The core 16-bit timer is designated T1, this section uses Tx to refer to timer T1 and all additional timers that
operate in exactly the same manner as timer T1, with the exception of the high speed capability described later.
Each timer block consists of a 16-bit timer, Tx, and two supporting 16-bit autoreload/capture registers, RxA and
RxB. Each timer block has two pins associated with it, TxA and TxB. The pin TxA supports I/O required by the
timer block, while the pin TxB is an input to the timer block. The timer block has three operating modes:
Processor Independent PWM mode, External Event Counter mode, and Input Capture mode.
The control bits TxC3, TxC2, and TxC1 allow selection of the different modes of operation.
Timer Operating Speeds
Each of the Tx timers, except T1, have the ability to operate at either the instruction cycle frequency (low speed)
or the internal clock frequency (MCLK). For 10 MHz CKI, the instruction cycle frequency is 2 MHz and the
internal clock frequency is 20 MHz. This feature is controlled by the High Speed Timer Control Register, HSTCR.
Its format is shown below. To place a timer, Tx, in high speed mode, set the appropriate TxHS bit to 1. For low
speed operation, clear the appropriate TxHS bit to 0. This register is cleared to 00 on Reset.
The T2IDLE bit is used to allow T2 operation while the device is in Idle mode. See TIMER T2 OPERATION IN
IDLE MODE for further information.
Bit 7
T2IDLE
Bit 6
0
Bit 5
0
HSTCR
Bit 4
Bit 3
0
0
Bit 2
0
Bit
1
T3HS
Bit
0
T2HS
Mode 1. Processor Independent PWM Mode
One of the timer's operating modes is the Processor Independent PWM mode. In this mode, the timers generate
a “Processor Independent” PWM signal because once the timer is set up, no more action is required from the
CPU which translates to lower software overhead and greater throughput. The user software services the timer
block only when the PWM parameters require updating. This capability is provided by the fact that the timer has
two separate 16-bit reload registers. One of the reload registers contains the “ON” time while the other holds the
“OFF” time. By contrast, a microcontroller that has only a single reload register requires an additional software to
update the reload value (alternate between the on-time/off-time).
The timer can generate the PWM output with the width and duty cycle controlled by the values stored in the
reload registers. The reload registers control the countdown values and the reload values are automatically
written into the timer when it counts down through 0, generating interrupt on each reload. Under software control
and with minimal overhead, the PWM outputs are useful in controlling motors, triacs, the intensity of displays,
and in providing inputs for data acquisition and sine wave generators.
In this mode, the timer Tx counts down at a fixed rate of t_C (T2 and T3 may be selected to operate from MCLK).
Upon every underflow the timer is alternately reloaded with the contents of supporting registers, RxA and RxB.
The very first underflow of the timer causes the timer to reload from the register RxA. Subsequent underflows
cause the timer to be reloaded from the registers alternately beginning with the register RxB.
Figure 17 shows a block diagram of the timer in PWM mode.
The underflows can be programmed to toggle the TxA output pin. The underflows can also be programmed to
generate interrupts.
Underflows from the timer are alternately latched into two pending flags, TxPNDA and TxPNDB. The user must
reset these pending flags under software control. Two control enable flags, TxENA and TxENB, allow the
interrupts from the timer underflow to be enabled or disabled. Setting the timer enable flag TxENA will cause an
interrupt when a timer underflow causes the RxA register to be reloaded into the timer. Setting the timer enable
flag TxENB will cause an interrupt when a timer underflow causes the RxB register to be reloaded into the timer.
Resetting the timer enable flags will disable the associated interrupts.
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