COP8AME9_14 Datasheet, PDF (62/102 Pages) Texas Instruments – COP8AME9 8-Bit CMOS Flash Microcontroller with 8k Memory, Dual Op Amps, Virtual EEPROM, Temperature Sensor, 10-Bit A/D and Brownout Reset

COP8AME9, COP8ANE9
SNOS930F – MARCH 2001 – REVISED MARCH 2013
www.ti.com
Mode Select
This 1-bit field is used to select the mode of operation (single ended or differential) as shown in the following
Table 26.
ADMOD
0
1
Table 26. A/D Conversion Mode Selection
Mode
Single Ended mode. This mode is required if the temperature sensor is being selected.
Differential mode (programmable gain amplifier must be bypassed)
Prescaler Select
This 1-bit field is used to select one of two prescaler clocks for the A/D Converter. The following Table 27 shows
the various prescaler options. Care must be taken, when selecting this bit, to not exceed the maximum frequency
of the A/D converter.
Table 27. A/D Converter Clock Prescale
PSC
0
1
Clock Select
MCLK Divide by 1
MCLK Divide by 16
Busy Bit
The ADBSY bit of the ENAD register is used to control starting and stopping of the A/D conversion. When
ADBSY is cleared, the prescale logic is disabled and the A/D clock is turned off, drawing minimal power. Setting
the ADBSY bit starts the A/D clock and initiates a conversion based on the values currently in the ENAD register.
Normal completion of an A/D conversion clears the ADBSY bit and turns off the A/D Converter.
When changing the channel and gain of the programmable gain amplifier, it is necessary to wait before
performing an A/D conversion. This due to the amplifier settling time. See the section on the Programmable Gain
Amplifier for these settling times.
If the user wishes to restart a conversion which is already in progress, this can be accomplished only by writing a
zero to the ADBSY bit to stop the current conversion and then by writing a one to ADBSY to start a new
conversion. This can be done in two consecutive instructions.
All multiplexor input channels should be internally gated off when ADBSY = 0, unless MUX =1 or the
programmable gain amplifier is enabled. When MUX =1 or the programmable gain amplifier is enabled, the
internal path through the multiplexor to the pin and the input path for the A/D Converter should be enabled.
A/D Result Registers
There are two result registers for the A/D converter: the high 8 bits of the result and the low 2-bits of the result.
The format of these registers is shown in Table 28 Table 29. Both registers are read/write registers, but in normal
operation, the hardware writes the value into the register when the conversion is complete and the software
reads the value. Both registers are undefined upon Reset. They hold the previous value until a new conversion
overwrites them. When reading ADRSTL, bits 5-0 will read as 0.
Bit 7
Bit 9
Bit 6
Bit 8
Bit 5
Bit 7
Table 28. ADRSTH
Bit 4
Bit 6
Bit 3
Bit 5
Bit 2
Bit 4
Bit 1
Bit 3
Bit 0
Bit 2
Bit 7
Bit 1
Bit 6
Bit 0
Table 29. ADRSTL
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
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