COP8AME9_14 Datasheet, PDF (51/102 Pages) Texas Instruments – COP8AME9 8-Bit CMOS Flash Microcontroller with 8k Memory, Dual Op Amps, Virtual EEPROM, Temperature Sensor, 10-Bit A/D and Brownout Reset

COP8AME9, COP8ANE9
www.ti.com
SNOS930F – MARCH 2001 – REVISED MARCH 2013
PEN: This bit enables/disables Parity (7- and 8-bit modes only). Read/Write, cleared on reset.
PEN = 0 Parity disabled.
PEN = 1 Parity enabled.
PSEL1, PSEL0: Parity select bits. Read/Write, cleared on reset.
PSEL1 = 0, PSEL0 = 0 Odd Parity (if Parity enabled)
PSEL1 = 0, PSEL1 = 1 Even Parity (if Parity enabled)
PSEL1 = 1, PSEL0 = 0 Mark(1) (if Parity enabled)
PSEL1 = 1, PSEL1 = 1 Space(0) (if Parity enabled)
XBIT9/PSEL0: Programs the ninth bit for transmission when the USART is operating with nine data bits per
frame. For seven or eight data bits per frame, this bit in conjunction with PSEL1 selects parity. Read/Write,
cleared on reset.
CHL1, CHL0: These bits select the character frame format. Parity is not included and is generated/verified by
hardware. Read/Write, cleared on reset.
CHL1 = 0, CHL0 = 0 The frame contains eight data bits.
CHL1 = 0, CHL0 = 1 The frame contains seven data bits.
CHL1 = 1, CHL0 = 0 The frame contains nine data bits.
CHL1 = 1, CHL0 = 1 Loopback Mode selected. Transmitter output internally looped back to receiver input. Nine
bit framing format is used.
ERR: This bit is a global USART error flag which gets set if any or a combination of the errors (DOE, FE, PE,
BO) occur. Read only; it cannot be written by software, cleared on reset.
RBFL: This bit is set when the USART has received a complete character and has copied it into the RBUF
register. It is automatically reset when software reads the character from RBUF. Read only; it cannot be written
by software, cleared on reset.
TBMT: This bit is set when the USART transfers a byte of data from the TBUF register into the TSFT register for
transmission. It is automatically reset when software writes into the TBUF register. Read only, bit is set to “one”
on reset; it cannot be written by software.
ENUR—USART RECEIVE CONTROL AND STATUS REGISTER (Address at 0BB)
DOE
FE
PE
BD
RBIT9
ATTN
XMTG
RCVG
Bit 7
Bit 0
DOE: Flags a Data Overrun Error. Read only, cleared on read, cleared on reset.
DOE = 0 Indicates no Data Overrun Error has been detected since the last time the ENUR register was read.
DOE = 1 Indicates the occurrence of a Data Overrun Error.
FE: Flags a Framing Error. Read only, cleared on read, cleared on reset.
FE = 0 Indicates no Framing Error has been detected since the last time the ENUR register was read.
FE = 1 Indicates the occurrence of a Framing Error.
PE: Flags a Parity Error. Read only, cleared on read, cleared on reset.
PE = 0 Indicates no Parity Error has been detected since the last time the ENUR register was read.
PE = 1 Indicates the occurrence of a Parity Error.
BD: Flags a line break.
BD = 0 Indicates no Line Break has been detected since the last time the ENUR register was read.
BD = 1 Indicates the occurrence of a Line Break.
Copyright © 2001–2013, Texas Instruments Incorporated
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