COP8AME9_14 Datasheet, PDF (76/102 Pages) Texas Instruments – COP8AME9 8-Bit CMOS Flash Microcontroller with 8k Memory, Dual Op Amps, Virtual EEPROM, Temperature Sensor, 10-Bit A/D and Brownout Reset

COP8AME9, COP8ANE9
SNOS930F – MARCH 2001 – REVISED MARCH 2013
www.ti.com
The lower limit of the service window is fixed at 2048 Idle Timer Clocks. Bits 7 and 6 of the WDSVR register
allow the user to pick an upper limit of the service window.
Table 37 shows the four possible combinations of lower and upper limits for the WATCHDOG service window.
This flexibility in choosing the WATCHDOG service window prevents any undue burden on the user software.
Bits 5, 4, 3, 2 and 1 of the WDSVR register represent the 5-bit Key Data field. The key data is fixed at 01100. Bit
0 of the WDSVR Register is the Clock Monitor Select bit.
WDSVR
Bit 7
0
0
1
1
X
X
WDSVR
Bit 6
0
1
0
1
X
X
Table 37. WATCHDOG Service Window Select
Clock
Monitor
Bit 0
X
X
X
X
0
1
Service Window
for High Speed Mode
(Lower-Upper Limits)
2048-8k t_C Cycles
2048-16k t_C Cycles
2048-32k t_C Cycles
2048-64k t_C Cycles
Clock Monitor Disabled
Clock Monitor Enabled
Service Window
for Dual Clock & Low Speed Modes
(Lower-Upper Limits)
2048-8k Cycles of 32 kHz Clk
2048-16k Cycles of 32 kHz Clk
2048-32k Cycles of 32 kHz Clk
2048-64k Cycles of 32 kHz Clk
Clock Monitor Disabled
Clock Monitor Enabled
CLOCK MONITOR
The Clock Monitor aboard the device can be selected or deselected under program control. The Clock Monitor is
specified not to reject the clock if the instruction cycle clock (1/t_C) is greater or equal to 5 kHz. This equates to a
clock input rate on the selected oscillator of greater or equal to 25 kHz.
WATCHDOG/CLOCK MONITOR OPERATION
The WATCHDOG is enabled by bit 2 of the Option register. When this Option bit is 0, the WATCHDOG is
enabled and pin G1 becomes the WATCHDOG output with a weak pull-up.
The WATCHDOG and Clock Monitor are disabled during reset. The device comes out of reset with the
WATCHDOG armed, the WATCHDOG Window Select bits (bits 6, 7 of the WDSVR Register) set, and the Clock
Monitor bit (bit 0 of the WDSVR Register) enabled. Thus, a Clock Monitor error will occur after coming out of
reset, if the instruction cycle clock frequency has not reached a minimum specified value, including the case
where the oscillator fails to start.
The WDSVR register can be written to only once after reset and the key data (bits 5 through 1 of the WDSVR
Register) must match to be a valid write. This write to the WDSVR register involves two irrevocable choices: (i)
the selection of the WATCHDOG service window (ii) enabling or disabling of the Clock Monitor. Hence, the first
write to WDSVR Register involves selecting or deselecting the Clock Monitor, select the WATCHDOG service
window and match the WATCHDOG key data. Subsequent writes to the WDSVR register will compare the value
being written by the user to the WATCHDOG service window value, the key data and the Clock Monitor Enable
(all bits) in the WDSVR Register. Table 38 shows the sequence of events that can occur.
The user must service the WATCHDOG at least once before the upper limit of the service window expires. The
WATCHDOG may not be serviced more than once in every lower limit of the service window.
When jumping to the boot ROM for ISP and virtual E2 operations, the hardware will disable the lower window
error and perform an immediate WATCHDOG service. The ISP routines will service the WATCHDOG within the
selected upper window. The ISP routines will service the WATCHDOG immediately prior to returning execution
back to the user's code in flash. Therefore, after returning to flash memory, the user can service the
WATCHDOG anytime following the return from boot ROM, but must service it within the selected upper window
to avoid a WATCHDOG error.
The WATCHDOG has an output pin associated with it. This is the WDOUT pin, on pin 1 of the port G. WDOUT is
active low. The WDOUT pin has a weak pull-up in the inactive state. Upon triggering the WATCHDOG, the logic
will pull the WDOUT (G1) pin low for an additional 16–32 cycles after the signal level on WDOUT pin goes below
the lower Schmitt trigger threshold. After this delay, the device will stop forcing the WDOUT output low. The
WATCHDOG service window will restart when the WDOUT pin goes high.
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