COP8AME9_14 Datasheet, PDF (80/102 Pages) Texas Instruments – COP8AME9 8-Bit CMOS Flash Microcontroller with 8k Memory, Dual Op Amps, Virtual EEPROM, Temperature Sensor, 10-Bit A/D and Brownout Reset

COP8AME9, COP8ANE9
SNOS930F – MARCH 2001 – REVISED MARCH 2013
www.ti.com
The user must set the BUSY flag immediately upon entering the Slave mode. This ensures that all data bits sent
by the Master is shifted properly. After eight clock pulses the BUSY flag is clear, the shift clock is stopped, and
the sequence may be repeated.
Figure 36. MICROWIRE/PLUS Application
Alternate SK Phase Operation and SK Idle Polarity
The device allows either the normal SK clock or an alternate phase SK clock to shift data in and out of the SIO
register. In both the modes the SK idle polarity can be either high or low. The polarity is selected by bit 5 of Port
G data register. In the normal mode data is shifted in on the rising edge of the SK clock and the data is shifted
out on the falling edge of the SK clock. The SIO register is shifted on each falling edge of the SK clock. In the
alternate SK phase operation, data is shifted in on the falling edge of the SK clock and shifted out on the rising
edge of the SK clock. Bit 6 of Port G configuration register selects the SK edge.
A control flag, SKSEL, allows either the normal SK clock or the alternate SK clock to be selected. Refer to
Table 41 for the appropriate setting of the SKSEL bit. The SKSEL is mapped into the G6 configuration bit. The
SKSEL flag will power up in the reset condition, selecting the normal SK signal provided the SK Idle Polarity
remains LOW.
SK Phase
Normal
Alternate
Alternate
Normal
Table 41. MICROWIRE/PLUS Shift Clock Polarity and Sample/Shift Phase
Port G
G6 (SKSEL) G5 Data Bit
Config. Bit
0
0
1
0
0
1
1
1
SO Clocked Out On:
SK Falling Edge
SK Rising Edge
SK Rising Edge
SK Falling Edge
SI Sampled On:
SK Rising Edge
SK Falling Edge
SK Falling Edge
SK Rising Edge
SK Idle Phase
Low
Low
High
High
Figure 37. MICROWIRE/PLUS SPI Mode Interface Timing, Normal SK Mode, SK Idle Phase being Low
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