COP8AME9_14 Datasheet, PDF (47/102 Pages) Texas Instruments – COP8AME9 8-Bit CMOS Flash Microcontroller with 8k Memory, Dual Op Amps, Virtual EEPROM, Temperature Sensor, 10-Bit A/D and Brownout Reset

COP8AME9, COP8ANE9
www.ti.com
SNOS930F – MARCH 2001 – REVISED MARCH 2013
Entering The Low Speed Halt Mode
The device enters the HALT mode under software control when the Port G data register bit 7 is set to 1. All
processor action stops in the middle of the next instruction cycle, and power consumption is reduced to a very
low level. In order to expedite exit from HALT, the low speed oscillator is left running when the device is Halted in
the Low Speed mode. However, the IDLE Timer will not be clocked.
Exiting The Low Speed Halt Mode
When the HALT mode is entered by setting bit 7 of the Port G data register, there is a choice of methods for
exiting the HALT mode: a chip Reset using the RESET pin or a Multi-Input Wake-up. The Reset method and
Multi-Input Wake-up method can be used with any clock option, but the availability of the G7 input is dependent
on the clock option.
HALT Exit Using Reset
A device Reset, which is invoked by a low-level signal on the RESET input pin, takes the device out of the Low
Speed mode and puts it into the High Speed mode.
HALT Exit Using Multi-Input Wake-up
The device can be brought out of the HALT mode by a transition received on one of the available Wake-up pins.
The pins used and the types of transitions sensed on the Multi-input pins are software programmable. For
information on programming and using the Multi-Input Wake-up feature, refer to the Multi-Input Wake-up section.
As the low speed oscillator is left running, there is no start up delay when exiting the low speed halt mode,
regardless of the state of the CLKDLY bit.
Note: To ensure accurate operation upon start-up of the device using Multi-Input Wake-up, the instruction in the
application program used for entering the HALT mode should be followed by two consecutive NOP (no-
operation) instructions.
Options
This device has two options associated with the HALT mode. The first option enables the HALT mode feature,
while the second option disables HALT mode operation. Selecting the disable HALT mode option will cause the
microcontroller to ignore any attempts to HALT the device under software control. See the Option section for
more details on this option bit.
Low Speed Idle Mode
In the IDLE mode, program execution stops and power consumption is reduced to a very low level as with the
HALT mode. However, the low speed oscillator, IDLE Timer (Timer T0), and Clock Monitor continue to operate,
allowing real time to be maintained. The device remains IDLE for a selected amount of time up to 2 seconds, and
then automatically exits the IDLE mode and returns to normal program execution using the low speed clock.
The device is placed in the IDLE mode under software control by setting the IDLE bit (bit 6 of the Port G data
register).
The IDLE Timer window is selectable from one of five values, 0.125 seconds, 0.25 seconds, 0.5 seconds, 1
second, and 2 seconds. Selection of this value is made through the ITMR register.
The IDLE mode uses the on-chip IDLE Timer (Timer T0) to keep track of elapsed time in the IDLE state. The
IDLE Timer runs continuously at the low speed clock rate, whether or not the device is in the IDLE mode. Each
time the bit of the timer associated with the selected window toggles, the T0PND bit is set, an interrupt is
generated (if enabled), and the device exits the IDLE mode if in that mode. If the IDLE Timer interrupt is enabled,
the interrupt is serviced before execution of the main program resumes. (However, the instruction which was
started as the part entered the IDLE mode is completed before the interrupt is serviced. This instruction should
be a NOP which should follow the enter IDLE instruction.) The user must reset the IDLE Timer pending flag
(T0PND) before entering the IDLE mode.
As with the HALT mode, this device can also be returned to normal operation with a Multi-Input Wake-up input.
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