COP8AME9_14 Datasheet, PDF (59/102 Pages) Texas Instruments – COP8AME9 8-Bit CMOS Flash Microcontroller with 8k Memory, Dual Op Amps, Virtual EEPROM, Temperature Sensor, 10-Bit A/D and Brownout Reset

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COP8AME9, COP8ANE9
SNOS930F – MARCH 2001 – REVISED MARCH 2013
Figure 27. Simplified A/D Converter Block Diagram
The A/D Converter supports both Single Ended and Differential modes of operation. Differential mode is only
supported when the programmable gain amplifier is bypassed.
Two specific analog channel selection modes are supported. These are as follows:
1. Allow any specific channel, except for the temperature sensor input, with or without the programmable gain
amplifier, to be selected at one time. The A/D Converter performs the specific conversion requested and
stops. When using the temperature sensor, the programmable gain amplifier is required. See the
Temperature Sensor section for more details on using the temperature sensor.
2. Allow any differential channel pair to be selected at one time. The A/D Converter performs the specific
differential conversion requested and stops. Differential mode is only supported when the programmable gain
amplifier is bypassed.
In both Single Ended mode and Differential mode, there is the capability to connect the analog multiplexor
output, with the exception of the temperature sensor input, and A/D converter input to external pins. This
provides the ability to externally connect a common filter/signal conditioning circuit for the A/D Converter.
The A/D Converter is supported by six memory mapped registers: two result registers, the control register, two
offset trimming registers, and the gain register. When the device is reset, the mode control register (ENAD) is
cleared, the A/D is powered down and the A/D result registers have unknown data. The offset trim registers are
also initialized to 40 Hex on Reset and need to be re-trimmed, if being used. The gain register is initialized to 00
on Reset.
A/D Control Register
The control register, ENAD contains 4 bits for channel selection, 1 bit for mode selection, 1 bit for the multiplexor
output selection, 1 bit for prescaler selection, and a Busy bit. An A/D conversion is initiated by setting the ADBSY
bit in the ENAD control register. The result of the conversion is available to the user in the A/D result registers,
ADRSTH and ADRSTL, when ADBSY is cleared by the hardware on completion of the conversion.
Bit 7
ADCH3
Bit 6
Bit 5
Channel Select
ADCH2
ADCH1
Table 23. ENAD Register
Bit 4
ADCH0
Bit 3
Mode Select
ADMOD
Bit 2
Mux/Out
MUX
Bit 1
Prescale
PSC
Bit 0
Busy
ADBSY
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