COP8AME9_14 Datasheet, PDF (15/102 Pages) Texas Instruments – COP8AME9 8-Bit CMOS Flash Microcontroller with 8k Memory, Dual Op Amps, Virtual EEPROM, Temperature Sensor, 10-Bit A/D and Brownout Reset

COP8AME9, COP8ANE9
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SNOS930F – MARCH 2001 – REVISED MARCH 2013
Functional Description
The architecture of the device is a modified Harvard architecture. With the Harvard architecture, the program
memory (Flash) is separate from the data store memory (RAM). Both Program Memory and Data Memory have
their own separate addressing space with separate address buses. The architecture, though based on the
Harvard architecture, permits transfer of data from Flash Memory to RAM.
CPU REGISTERS
The CPU can do an 8-bit addition, subtraction, logical or shift operation in one instruction (t_C) cycle time.
There are six CPU registers:
A is the 8-bit Accumulator Register
PC is the 15-bit Program Counter Register
PU is the upper 7 bits of the program counter (PC)
PL is the lower 8 bits of the program counter (PC)
B is an 8-bit RAM address pointer, which can be optionally post auto incremented or decremented.
X is an 8-bit alternate RAM address pointer, which can be optionally post auto incremented or decremented.
S is the 8-bit Data Segment Address Register used to extend the lower half of the address range (00 to 7F) into
256 data segments of 128 bytes each.
SP is the 8-bit stack pointer, which points to the subroutine/interrupt stack (in RAM). With reset the SP is
initialized to RAM address 06F Hex. The SP is decremented as items are pushed onto the stack. SP points to
the next available location on the stack.
All the CPU registers are memory mapped with the exception of the Accumulator (A) and the Program Counter
(PC).
PROGRAM MEMORY
The program memory consists of 8192 bytes of Flash Memory. These bytes may hold program instructions or
constant data (data tables for the LAID instruction, jump vectors for the JID instruction, and interrupt vectors for
the VIS instruction). The program memory is addressed by the 15-bit program counter (PC). All interrupts in the
device vector to program memory location 00FF Hex. The contents of the program memory read 00 Hex in the
erased state. Program execution starts at location 0 after RESET.
If a Return instruction is executed when the SP contains 6F (hex), instruction execution will continue from
Program Memory location 1FFF (hex). If location 1FFF is accessed by an instruction fetch, the Flash Memory will
return a value of 00. This is the opcode for the INTR instruction and will cause a Software Trap.
For the purpose of erasing and rewriting the Flash Memory, it is organized in pages of 64 bytes.
Refer to Table 3 for program memory size and available address ranges.
Device
COP8AME9
Table 3. Available Memory Address Ranges
Program Memory
Size (Flash)
8192
Flash Memory
Page Size
(Bytes)
64
Option Register
Address (Hex)
1FFF
Data Memory
Size (RAM)
512
Segments
Available
0-3
Maximum RAM
Address (HEX)
037F
DATA MEMORY
The data memory address space includes the on-chip RAM and data registers, the I/O registers (Configuration,
Data and Pin), the control registers, the MICROWIRE/PLUS SIO shift register, and the various registers, and
counters associated with the timers and the USART (with the exception of the IDLE timer). Data memory is
addressed directly by the instruction or indirectly by the B, X and SP pointers.
Copyright © 2001–2013, Texas Instruments Incorporated
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