COP8AME9_14 Datasheet, PDF (27/102 Pages) Texas Instruments – COP8AME9 8-Bit CMOS Flash Microcontroller with 8k Memory, Dual Op Amps, Virtual EEPROM, Temperature Sensor, 10-Bit A/D and Brownout Reset

COP8AME9, COP8ANE9
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SNOS930F – MARCH 2001 – REVISED MARCH 2013
ISP Address Registers
The address registers (ISPADHI & ISPADLO) are used to specify the address of the byte of data being written or
read. For page erase operations, the address of the beginning of the page should be loaded. For mass erase
operations, 0000 must be placed into the address registers. When reading the Option register, FFFF (hex)
should be placed into the address registers. Registers ISPADHI and ISPADLO are cleared to 00 on Reset.
These registers can be loaded from either flash program memory or Boot ROM and must be maintained for the
entire duration of the operation.
Note: The actual memory address of the Option Register is 1FFF (hex), however the MICROWIRE/PLUS ISP
routines require the address FFFF (hex) to be used to read the Option Register when the Flash Memory is
secured.
Bit 7
Addr 15
Bit 6
Addr 14
Table 6. High Byte of ISP Address
Bit 5
Addr 13
ISPADHi
Bit 4
Bit 3
Addr 12
Addr 11
Bit 2
Addr 10
Bit 1
Addr 9
Bit 0
Addr 8
Bit 7
Addr 7
Bit 6
Addr 6
Table 7. Low Byte of ISP Address
Bit 5
Addr 5
ISPADLO
Bit 4
Bit 3
Addr 4
Addr 3
Bit 2
Addr 2
Bit 1
Addr 1
Bit 0
Addr 0
ISP Read Data Register
The Read Data Register (ISPRD) contains the value read back from a read operation. This register can be
accessed from either flash program memory or Boot ROM. This register is undefined on Reset.
Bit 7
Bit7
Bit 6
Bit6
Table 8. ISP Read Data Register
Bit 5
Bit5
ISPRD
Bit 4
Bit 3
Bit4
Bit3
Bit 2
Bit2
Bit 1
Bit1
Bit 0
Bit0
ISP Write Data Register
The Write Data Register (ISPWR) contains the data to be written into the specified address. This register is
undetermined on Reset. This register can be accessed from either flash program memory or Boot ROM. The
Write Data register must be maintained for the entire duration of the operation.
Bit 7
Bit7
Bit 6
Bit6
Table 9. ISP Write Data Register
Bit 5
Bit5
ISPWR
Bit 4
Bit 3
Bit4
Bit3
Bit 2
Bit2
Bit 1
Bit1
Bit 0
Bit0
ISP Write Timing Register
The Write Timing Register (PGMTIM) is used to control the width of the timing pulses for write and erase
operations. The value to be written into this register is dependent on the frequency of CKI and is shown in
Table 10. This register must be written before any write or erase operation can take place. It only needs to be
loaded once, for each value of CKI frequency. This register can be loaded from either flash program memory or
Boot ROM and must be maintained for the entire duration of the operation. The MICROWIRE/PLUS ISP routine
that is resident in the boot ROM requires that this Register be defined prior to any access to the Flash memory.
Refer to section MICROWIRE/PLUS ISP for more information on available ISP commands. On Reset, the
PGMTIM register is loaded with the value that corresponds to 10 MHz frequency for CKI.
Copyright © 2001–2013, Texas Instruments Incorporated
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