COP8AME9_14 Datasheet, PDF (20/102 Pages) Texas Instruments – COP8AME9 8-Bit CMOS Flash Microcontroller with 8k Memory, Dual Op Amps, Virtual EEPROM, Temperature Sensor, 10-Bit A/D and Brownout Reset

COP8AME9, COP8ANE9
SNOS930F – MARCH 2001 – REVISED MARCH 2013
www.ti.com
ADRSTL: RANDOM
Op Amp:
AMPTRMN, AMPTRMP: Cleared, except bit 6 = 1
ADGAIN: CLEARED
ISP CONTROL:
ISPADLO: CLEARED
ISPADHI: CLEARED
PGMTIM: PRESET TO VALUE FOR 10 MHz CKI
WATCHDOG (if enabled):
The device comes out of reset with both the WATCHDOG logic and the Clock Monitor detector armed,
with the WATCHDOG service window bits set and the Clock Monitor bit set. The WATCHDOG and Clock
Monitor circuits are inhibited during reset. The WATCHDOG service window bits being initialized high
default to the maximum WATCHDOG service window of 64k T0 clock cycles. The Clock Monitor bit being
initialized high will cause a Clock Monitor error following reset if the clock has not reached the minimum
specified frequency at the termination of reset. A Clock Monitor error will cause an active low error output
on pin G1. This error output will continue until 16–32 T0 clock cycles following the clock frequency
reaching the minimum specified value, at which time the G1 output will go high.
External Reset
The RESET input, when pulled low, initializes the device. The RESET pin must be held low for a minimum of one
instruction cycle to ensure a valid reset.
RESET may also be used to cause an exit from the HALT mode.
A recommended reset circuit for this device is shown in Figure 9.
Figure 9. Reset Circuit Using External Reset
On-Chip Brownout Reset
The device generates an internal reset as V_CC rises. While V_CC is less than the specified brownout voltage (V_bor),
the device is held in the reset condition and the Idle Timer is preset with 00Fx (240–256 t_C). When V_CC reaches a
value greater than V_bor, the Idle Timer starts counting down. Upon underflow of the Idle Timer, the internal reset
is released and the device will start executing instructions. This internal reset will perform the same functions as
external reset. Once V_CC is above V_bor, and this initial Idle Timer time-out takes place, instruction execution
begins and the Idle Timer can be used normally. If, however, V_CC drops below V_bor, an internal reset is
generated, and the Idle Timer is preset with 00Fx. The device now waits until V_CC is greater than V_bor and the
countdown starts over. The functional operation of the device is specified down to the V_bor level.
One exception to the above is that the brownout circuit will insert a delay of approximately 3 ms on power up or
any time the V_CC drops below a voltage of about 1.8V. The device will be held in Reset for the duration of this
delay before the Idle Timer starts counting the 240 to 256 t_C. This delay starts as soon as the V_CC rises above
the trigger voltage (approximately 1.8V). This behavior is shown in Figure 10.
In Case 1, V_CC rises from 0V and the on-chip RESET is undefined until the supply is greater than approximately
1.0V. At this time the brownout circuit becomes active and holds the device in RESET. As the supply passes a
level of about 1.8V, a delay of about 3 ms (t_d) is started and the Idle Timer is preset to a value between 00F0
and 00FF (hex). Once V_CC is greater than V_bor and t_d has expired, the Idle Timer is allowed to count down (t_id).
20
Submit Documentation Feedback
Copyright © 2001–2013, Texas Instruments Incorporated
Product Folder Links: COP8AME9 COP8ANE9