CDCE62005 Datasheet, PDF (8/76 Pages) Texas Instruments – Five/Ten Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs

CDCE62005
SCAS862 – NOVEMBER 2008........................................................................................................................................................................................... www.ti.com
Output Block
Each of the five identical output blocks incorporates an output multiplexer, a clock divider module, and a
universal output array as shown.
Output
MUX
Control
Sync
Pulse
Enable
Output Buffer Control
PRI_IN
SEC_IN
SMART_MUX
SYNTH
Digital Phase Adjust (7 -bits )
/1,2,3,4,5Clock D/i1vi-de/8r Module 0/2- 4
UxP
LVDS
UxN
LVPECL
Figure 6. CDCE62005 Output Block (1 of 5)
Clock Divider Module 0–4
The following shows a simplified version of a Clock Divider Module (CDM). If an individual clock output channel
is not used, then the user should disable the CDM and Output Buffer for the unused channel to save device
power. Each channel includes two 7-bit registers to control the divide ratio used and the clock phase for each
output. The output divider supports divide ratios from divide by 1 (bypass the divider) to divide by 80; the divider
does not support all integer values between 1 and 80. Refer to Table 23 for a complete list of divide ratios
supported.
Sync Pulse
(internally generated)
From
Output
MUX
Enable
Digital Phase Adjust (7-bits)
Output Divider (7-bits)
To
Output
Buffer
Figure 7. CDCE62005 Output Divider Module (1 of 5)
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