CDCE62005 Datasheet, PDF (68/76 Pages) Texas Instruments – Five/Ten Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs

CDCE62005
SCAS862 – NOVEMBER 2008........................................................................................................................................................................................... www.ti.com
APPLICATION INFORMATION AND GENERAL USAGE HINTS
Fan-out Buffer
Each output of the CDCE62005 can be configured as a fan-out buffer (divider bypassed) or fan-out buffer with
divide and skew control functionality.
Divide by 1: Up to 1500 MHz
Otherwise : Up to 1175 MHz
PRI_IN
SEC _IN
/1 - /80
/1 - /80
U0P
U0N
U4P
U4N
Up to 5 Outputs :
LVPECL or LVDS
Up to 10 Outputs:
LVCMOS
Figure 41. CDCE62005 Fan-out Buffer Mode
Clock Generator
The CDCE62005 can generate 5–10 low noise clocks from a single crystal or crystal oscillator as follows:
XTAL /
AUX _IN
Smart
MUX
Feedback
Divider
Input
Divider
PFD /
CP
Prescaler
Output
Divider 0
U0P
U0N
Output
Divider 4
U4P
U4N
Figure 42. CDCE62005 Clock Generator Mode
Jitter Cleaner – Mixed Mode ⁽¹⁾
The following table presents a common scenario. The CDCE62005 must generate several integer-related clocks
from a reference that has traversed a backplane. In order for jitter cleaning to take place, the phase noise of the
on-board clock path must be better than that of the incoming clock. The designer must pay attention to the
optimization of the loop bandwidth of the synthesizer and understand the phase noise profiles of the oscillators
involved. Further, other devices on the card require clocks at frequencies not related to the backplane clock. The
system requires combinations of differential and single-ended clocks in specific formats with specific phase
relationships. ⁽¹⁾
CLOCK FREQUENCY
10.000 MHz
30.72 MHz
122.88 MHz
491.52 MHz
245.76 MHz
30.72 MHz
10.000 MHz
INPUT/OUTPUT
Input
Input
Output
Output
Output
Outputs
Outputs
FORMAT
LVDS
LVDS
LVDS
LVPECL
LVPECL
LVCMOS
LVCMOS
NUMBER
1
1
1
1
1
2
2
CDCE62005 PORT
SEC_IN
PRI_IN
U0
U1
U2
U3
U4
COMMENT
Low end crystal oscillator
Reference from backplane
SERDES Clock
ASIC
FPGA
ASIC
CPU, DSP
(1) Pay special attention when using the universal inputs with two different clock sources. Two clocks derived from the same source may
use the internal bias generator and internal termination network without jitter performance degradation. However, if their origin is from
different sources (e.g. two independent oscillators) then sharing the internal bias generator can degrade jitter performance significantly.
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