CDCE62005 Datasheet, PDF (55/76 Pages) Texas Instruments – Five/Ten Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs

CDCE62005
www.ti.com........................................................................................................................................................................................... SCAS862 – NOVEMBER 2008
SYNTHESIZER BLOCK
Figure 33 provides an overview of the CDCE62005 synthesizer block. The Synthesizer Block provides a Phase
Locked Loop, a partially integrated programmable loop filter, and two Voltage Controlled Oscillators (VCO). The
synthesizer block generates an output clock called “SYNTH” and drives it onto the Internal Clock Distribution
Bus.
Input Divider Settings
Register 5
21 20 19 18 17 16 15 14
Charge Pump Current
Register 6
19 18 17 16
Loop Filter Settings
Register 7
76543210
15 14 13 12 11 10 9 8
20 19 18 17 16
SMART _MUX
Feedback Divider
/8 - /1280
Input Divider
/1 - /256
/1,/2,/5,/8,/10,/16,/20
PFD /
CP
Register 6
10 9 8 7 6 5 4 3
Feedback Divider
Register 6
15 14 13
Feedback Bypass Divider
50 kHz –
400 kHz
1.75 GHz –
2.356 GHz
Prescaler
Register 6
21
Prescaler SYNTH
/2,/3,/4,/5
Register 6
0
VCO Select
Figure 33. CDCE62005 Synthesizer Block
Input Divider
The Input Divider divides the clock signal selected by the Smart Multiplexer (see Table 17) and presents the
divided signal to the Phase Frequency Detector / Charge Pump of the frequency synthesizer.
SELINDIV7
5.21
0
0
0
0
0
0
•
•
1
SELINDIV6
5.20
0
0
0
0
0
0
•
•
1
Table 31. CDCE62005 Input Divider Settings
SELINDIV5
5.19
0
0
0
0
0
0
•
•
1
INPUT DIVIDER SETTINGS
SELINDIV4 SELINDIV3
5.18
5.17
0
0
0
0
0
0
0
0
0
0
0
0
•
•
•
•
1
1
SELINDIV2
5.16
0
0
0
0
1
1
•
•
1
SELINDIV1
5.15
0
0
1
1
0
0
•
•
1
SELINDIV0
5.14
0
1
0
1
0
1
•
•
1
DIVIDE
RATIO
1
2
3
4
5
6
•
•
256
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