CDCE62005 Datasheet, PDF (36/76 Pages) Texas Instruments – Five/Ten Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs

CDCE62005
SCAS862 – NOVEMBER 2008........................................................................................................................................................................................... www.ti.com
Device Control
Figure 22 provides a conceptual explanation of the CDCE62005 Device operation. Table 14 defines how the
device behaves in each of the operational states.
Power ON
Reset
Power
Applied
Delay Finished
Device
OFF
Sleep
Sleep = OFF
Calibration
Hold
CAL_Enabled
Power Down
Sleep = ON
VCO
CAL
Power Down = ON
CAL Done
Manual
Recalibration = ON
Active Mode
Sync = ON
Sync = OFF
Sync
Figure 22. CDCE62005 Device State Control Diagram
Table 14. CDCE62005 Device State Definitions
State
Device Behavior
Entered Via
Exited Via
SPI Port
Power-On
Reset ⁽¹⁾
After device power supply reaches
approximately 2.35 V, the contents
of EEPROM are copied into the
Device Registers, thereby initializing
the device hardware.
Power applied to the device or upon
exit from Power Down State via the
Power_Down pin set HIGH.
Power On Reset and EEPROM loading
delays are finished OR the Power_Down
pin is set LOW.
Calibration
Hold
The device waits until either
ENCAL_MODE (Device Register 6
bit 27) is low (Start up calibration
enabled) or both ENCAL_MODE is
high (Manual Calibration Enabled)
AND ENCAL (Device Register 6 bit
22) transitions from a low to a high
signaling the device.
Delay process in the Power-On Reset
State is finished or Sleep Mode (Sleep
bit is in Register 8 bit 7) is turned OFF
while in the Sleep State. Power Down
must be OFF to enter the Calibration
Hold State.
The device waits until either
ENCAL_MODE (Device Register 6 bit 27)
is low (Start up calibration enabled) or
both ENCAL_MODE is high (Manual
Calibration Enabled) AND ENCAL (Device
Register 6 bit 22) transitions from a low to
a high signaling the device
VCO CAL
The voltage controlled oscillator is
calibrated based on the PLL settings
and the incoming reference clock.
After the VCO has been calibrated,
the device enters Active Mode
automatically.
Calibration Hold: CAL Enabled
becomes true when either
ENCAL_MODE (Device Register 6 bit
27) is low or both ENCAL_MODE is
high AND ENCAL (Device Register 6
bit 22) transitions from a low to a high.
Active Mode: A Manual Recalibration
is requested. This is initiated by
setting ENCAL_MODE to HIGH
(Manual Calibration Enabled) AND
initiating a calibration sequence by
applying a LOW to HIGH transition on
ENCAL.
Calibration Process in completed
Normal Operation
Active Mode
CAL Done (VCO calibration process
finished) or Sync = OFF (from Sync
State).
Sync, Power Down, Sleep, or Manual
Recalibration activated.
OFF
ON
ON
ON
Status
PLL
Output
Divider
Disabled Disabled
Enabled Disabled
Enabled Disabled
Enabled
Disabled
or
Enabled
Output
Buffer
OFF
OFF
OFF
Disabled
or
Enabled
(1) To ensure proper operation, independently from power supply ramp up, Power_Down pin should be held LOW for 50 µs after power
supply is stable.
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