CDCE62005 Datasheet, PDF (65/76 Pages) Texas Instruments – Five/Ten Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs

CDCE62005
www.ti.com........................................................................................................................................................................................... SCAS862 – NOVEMBER 2008
DEVICE POWER CALCULATION AND THERMAL MANAGEMENT
The CDCE62005 is a high performance device, therefore careful attention must be paid to device configuration
and printed circuit board layout with respect to power consumption. Table 44 provides the power consumption for
the individual blocks within the CDCE62005. To estimate total power consumption, calculate the sum of the
products of the number of blocks used and the power dissipated of each corresponding block.
Internal Block (Power at 3.3V)
Input Circuit
PLL and VCO Core
Output Divider
Output Buffer ( LVPECL)
Output Buffer (LVDS)
Output Buffer (LVCMOS)
Table 44. CDCE62005 Power Consumption
Power Dissipated per Block
18 mW
746 mW
185 mW
116 mW
76 mW
86 mW
Number of Blocks per Device
1
1
5
5
5
10
This power estimate determines the degree of thermal management required for a specific design. Employing the
thermally enhanced printed circuit board layout shown in Figure 39 insures that the thermal performance curves
shown in Figure 38 apply. Observing good thermal layout practices enables the thermal pad on the backside of
the QFN-48 package to provide a good thermal path between the die contained within the package and the
ambient air. This thermal pad also serves as the ground connection the device; therefore, a low inductance
connection to the ground plane is essential.
Figure 39 shows a layout optimized for good thermal performance and a good power supply connection as well.
The 7×7 filled via patter facilitates both considerations. Finally, the recommended layout achieves θ_JA =
27.3°C/W in still air and 20.3°C/W in an environment with 100 LFM airflow if implemented on a JEDEC compliant
thermal test board..
Die Temperature vs Total Device Power
RL 0 LFM 85 C
125
JEDEC 100 LFM 25 C
100
JDEC 0 LFM 85 C
RL 100 LFM 85 C
JEDEC 0 LFM 25 C
RL 0 LFM 25 C
75
JEDEC 100 LFM 85 C
RL 100 LFM 25 C
50
25
JEDEC 0 LFM 25 C
JEDEC 100 LFM 25 C
RL 0 LFM 25 C
RL 100 LFM 25 C
JEDEC 0 LFM 85 C
JEDEC 100 LFM 85 C
RL 0 LFM 85 C
RL 100 LFM 85 C
0
0
1
2
3
4
Power (W)
Figure 38. CDCE62005 Die Temperature vs Device Power
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s) :CDCE62005
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