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CDCE62005 Datasheet, PDF (46/76 Pages) Texas Instruments – Five/Ten Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs
CDCE62005
SCAS862 – NOVEMBER 2008........................................................................................................................................................................................... www.ti.com
Table23. CDCE62005 Output Divider Settings
OUTPUT DIVIDER n SETTINGSRegister n (n = 0,1,2,3,4)
Multiplexer
Integer Divider
Prescaler
Output Phase*
Output Divide Ratio
n.19 n.18 n.17 n.16 n.15 n.14 n.13 n.20
X
X
X
X
X
X
X
0
0
1
0
0
0
0
0
1
–
1
0
0
0
0
0
0
1
2
1
0
0
0
0
0
1
1
3
1
0
0
0
0
1
0
1
4
1
0
0
0
0
1
1
1
5
0
0
0
0
0
0
1
1
3
0
0
0
0
0
1
0
1
4
0
0
0
0
0
1
1
1
5
0
0
0
0
1
0
1
1
3
0
0
0
0
1
1
0
1
4
0
0
0
0
1
1
1
1
5
0
0
0
1
0
0
1
1
3
0
0
0
1
0
1
0
1
4
0
0
0
1
0
1
1
1
5
0
0
0
1
1
1
0
1
4
0
0
0
1
1
1
1
1
5
0
0
1
0
0
1
1
1
5
0
0
1
0
1
0
1
1
3
0
0
1
0
1
1
0
1
4
0
0
1
0
1
1
1
1
5
0
0
1
1
0
0
0
1
2
0
0
1
1
0
0
1
1
3
0
0
1
1
0
1
0
1
4
0
0
1
1
0
1
1
1
5
0
0
1
1
1
1
0
1
4
0
0
1
1
1
1
1
1
5
Output
Channels Auxiliary
Cycles Degree
0-4
Output
OFF
OFF
OFF
OFF
–
0
0
1
4
–
0.5
180
2**
4
–
0
0
3**
6
–
0.5
180
4
8
–
0
0
5
10
2
21
7560
6
6
2
28.5 10260
8
8
2
35
12500
10
10
4
24
8640
12
12
4
32.5 11700
16
16
4
40
14400
20
20
6
27
9720
18
18
6
36.5 13140
24
24
6
45
16200
30
30
8
40.5 14580
32
32
8
50
18000
40
40
10
55
19800
50
50
12
36
12960
36
36
12
48.5 17460
48
48
12
60
21600
60
60
14
25.5 9540
28
28
14
39
14040
42
42
14
52.5 18900
56
56
14
65
23400
70
70
16
56.5 20340
64
64
16
70
25200
80
80
*These columns show that the output divider generates a unique phase lag in the output clock (relative to the clock from the output multiplexer) determined by the
divide ratio used.
**Output channel 2 or 3 determine the auxiliary output divide ratio. For example, if the auxiliary output is programmed to drive via output 2 and output 2 divider is
programmed to divide by 3, then the divide ratio for the auxiliary output will be 6.
46
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