CDCE62005 Datasheet, PDF (41/76 Pages) Texas Instruments – Five/Ten Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs

CDCE62005
www.ti.com........................................................................................................................................................................................... SCAS862 – NOVEMBER 2008
Smart Multiplexer Auto Mode
Smart Multiplexer Auto Mode switches automatically between clock inputs based on a prioritization scheme
shown in Table 17. If using the Smart Multiplexer Auto Mode, the frequencies of the clock inputs may differ by up
to 20%. The phase relationship between clock inputs has no restriction. The smart multiplexer includes signal
conditioning that provides glitch suppression⁽¹⁾.
Upon the detection of a loss of signal on the highest priority clock, the smart multiplex switches its output to the
next highest priority clock on the first incoming rising edge of the next highest priority clock. During this switching
operation, the output of the smart multiplexer is low. Upon restoration of the higher priority clock, the smart
multiplexer waits until it detects four complete cycles from the higher priority clock prior to switching the output of
the smart multiplexer back to the higher priority clock. During this switching operation, the output of the smart
multiplexer remains high until the next falling edge as shown in Figure 25.
PRI _ REF
SEC _ REF
Internal
Reference Clock
Primary Clock
Secondary Clock
Primary Clock
Figure 25. CDCE62005 Smart Multiplexer Timing Diagram
Smart Multiplexer Dividers
Register 5
5432
REF_SEL
PRI_IN
Universal Input Buffers
SEC _IN
Smart MUX
Control
Register 0
10
/1:/2:HiZ
Smart Multiplexer
Smart
MUX 1
Register 1
10
/1:/2:HiZ
Reference Divider
/1 - /8
Register 3 Register 2
0 10
Smart
MUX2
XTAL /
AUX _IN
Auxiliary Input
Figure 26. CDCE62005 Smart Multiplexer
The CDCE62005 Smart Multiplexer Block provides the ability to divide the primary and secondary UIB or to
disconnect a UIB from the first state of the smart multiplexer altogether.
Bit Name →
Register.Bit →
Table 18. CDCE62005 Pre-Divider Settings
Primary Pre-Divider
DIV2PRIY
0.1
DIV2PRIX
0.0
0
0
0
1
Divide Ratio
Hi-Z
/2
Bit Name →
Register.Bit →
Secondary Pre-Divider
DIV2SECY
1.1
DIV2SECX
1.0
0
0
0
1
Divide Ratio
Hi-Z
/2
(1) This implementation does not include a phase build-out mechanism.
Copyright © 2008, Texas Instruments Incorporated
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