CDCE62005 Datasheet, PDF (64/76 Pages) Texas Instruments – Five/Ten Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs

CDCE62005
SCAS862 – NOVEMBER 2008........................................................................................................................................................................................... www.ti.com
Analog Lock Detect
Figure 37 shows the Analog Lock Detect circuit. Depending upon the phase relationship of the two signals
presented at the PFD/CP inputs, the lock detect circuit either charges (if the PLL is locked) or discharges (if PLL
is unlocked) the circuit shown via 100µA current sources. An external capacitor determines the sensitivity of the
lock detect circuit. The value of the capacitor determines the rate of change of the voltage presented on the
output pin PLL_LOCK and hence how quickly the PLL_LOCK output toggles based on a change of PLL locked
status. The PLL_LOCK pin is an analog output in analog lock detect mode.
Vout
=
1
C
´
i´
t
(6)
Solving for t yields:
t = ^{Vout ´ C}
i
(7)
V_H = 0.55 × V_CC
V_L = 0.35 × V_CC
For Example, let:
C = 10 nF
V_cc = 3.3 V \ V_H @ 1.8 V = V_Out
t = ^1.8´10n @ 164 μs
110 μ
Vcc
110 uA
Lock_I
From Input Divider
From Feedback Divider
PFD/
CP
Locked
Unlocked _80k
PLL_LOCK
5 pF
To Host
C
110 uA
Figure 37. CDCE62005 Analog Lock Detect
64
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