CDCE62005 Datasheet, PDF (70/76 Pages) Texas Instruments – Five/Ten Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs

CDCE62005
SCAS862 – NOVEMBER 2008........................................................................................................................................................................................... www.ti.com
Data Converter Jitter Requirements
140
130
120
110
100
90
80
70
60
50
40
30
20
10
0
1
100 fs
50 fs
1 ps
350 fs
10
100
1000
Figure 44. Data Converter Jitter Requirements
26
24
22
20
18
16
14
12
10
8
6
4
2
0
10000
CDCE62005 SERDES Startup Mode
A common scenario involves a host communicating to a satellite system via a high-speed wired communications
link. Typical communications media might be a cable, backplane, or fiber. The reference clock for the satellite
system is embedded in the high speed link. This reference clock must be recovered by the SERDES, however,
the recovered clock contains unacceptable levels of jitter due to a degradation of SNR associated with
transmission over the media. At system startup, the satellite system must self-configure prior to the recovery and
cleanup of the reference clock provided by the host. Furthermore, upon loss of the communication link with the
host, the satellite system must continue to operate albeit with limited functionality. Figure 45 shows a block
diagram of an optical based system with such a mechanism that takes advantage of the features of the
CDCE62005:
Data
SERDES ^{Cleaned Clock}
Recovered Clock
CDCE 62005
ASIC Clock
ASIC
Figure 45. CDCE62005 SERDES Startup Overview
The functionality provided by the Smart Multiplexer provides a straightforward implementation of a SERDES
clock link. The Auxiliary Input provides a startup clock because it connects to a crystal. The on-chip EEPROM
determines the default configuration at power-up; therefore, the CDCE62005 requires no host communication to
begin cleaning the recovered clock once it is available. The CDCE62005 immediately begins clocking the
satellite components including the SERDES using the crystal as a clock source and a frequency reference. After
the SERDES recovers the clock, the CDCE62005 removes the jitter via the on-chip synthesizer/loop filter. The
recovered clock from the communications link becomes the frequency reference for the satellite system after the
smart multiplexer automatically switches over to it. The CDCE62005 applies the cleaned clock to the recovered
clock input on the SERDES; thereby establishing a reliable communications link between host and satellite
systems.
70
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