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CDCE62005 Datasheet, PDF (31/76 Pages) Texas Instruments – Five/Ten Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs
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CDCE62005
www.ti.com........................................................................................................................................................................................... SCAS862 – NOVEMBER 2008
Device Registers: Register 4
SPI RAM BIT NAME
BIT BIT
0
A0
1
A1
2
A2
3
A3
4
0 RESERVED
5
1 ATETEST
6
2 RESERVED
7
3 RESERVED
8
4 OUTMUX4SELX
9
5 OUTMUX4SELY
10 6 PH4ADJC0
11 7 PH4ADJC1
12 8 PH4ADJC2
13 9 PH4ADJC3
14 10 PH4ADJC4
15 11 PH4ADJC5
16 12 PH4ADJC6
17 13 OUT4DIVRSEL0
18 14 OUT4DIVRSEL1
19 15 OUT4DIVRSEL2
20 16 OUT4DIVRSEL3
21 17 OUT4DIVRSEL4
22 18 OUT4DIVRSEL5
23 19 OUT4DIVRSEL6
24 20 OUT4DIVSEL
25 21 HiSWINGLVPEC4
26 22 CMOSMODE4PX
27 23 CMOSMODE4PY
28 24 CMOSMODE4NX
29 25 CMOSMODE4NY
30 26 OUTBUFSEL4X
31 27 OUTBUFSEL4Y
Table 9. CDCE62005 Register 4 Bit Definitions
RELATED
BLOCK
—
TI Test Bit
Output 4
Output 4
Output 4
Output 4
Output 4
Output 4
Output 4
Output 4
Output 4
Output 4
Output 4
Output 4
Output 4
Output 4
Output 4
Output 4
Output 4
Output 4
Output 4
Output 4
Output 4
Output 4
Output 4
Output 4
DESCRIPTION/FUNCTION
Address 0
Address 1
Address 2
Address 3
This bit must be set to a “0”
0 (default): normal operation,
1: outputs have deterministic delay relative to low-to-high edge of SYNC pin
Used in Test Mode
Used in Test Mode
OUTPUT MUX “4” Select. Selects the Signal driving Output Divider”4”
(X,Y) = 00: PRI_IN, 01:SEC_IN, 10:SMART_MUX, 11:VCO_CORE
Coarse phase adjust select for output divider “4”
OUTPUT DIVIDER “4” Ratio Select
When set to “0”, the divider is disabled
When set to “1”, the divider is enabled
High Swing LVPECL When set to “1” and Normal Swing when set to “0”
– If LVCMOS or LVDS is selected the Output swing will stay at the same level.
– If LVPECL buffer is selected the Output Swing will be 30% higher if this bit is set to “1”
and Normal LVPECL if it is set to “0”.
LVCMOS mode select for OUTPUT “4” Positive Pin.
(X,Y)=00:Active, 10:Inverting, 11:Low, 01:3-State
LVCMOS mode select for OUTPUT “3” Negative Pin.
(X,Y)=00:Active, 10:Inverting, 11:Low, 01:3-State
OUTPUT TYPE
RAM BITS
22 23 24 25 26 27
LVPECL
00 0 0 0
1
LVDS
01 0 1 1
1
LVCMOS
See Settings Above* 0
0
Output Disabled
01 0 1 1
0
* Use Description for Bits 22,23,24 and 25 for setting the LVCMOS Outputs
0
0
1
0
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s) :CDCE62005
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