CDCE62005 Datasheet, PDF (29/76 Pages) Texas Instruments – Five/Ten Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs

CDCE62005
www.ti.com........................................................................................................................................................................................... SCAS862 – NOVEMBER 2008
Device Registers: Register 2
SPI RA BIT NAME
BIT M
BIT
0
A0
1
A1
2
A2
3
A3
4 0 REFDIV0
5 1 REFDIV1
6 2 RESERVED
7 3 RESERVED
8 4 OUTMUX2SELX
9 5 OUTMUX2SELY
10 6 PH2ADJC0
11 7 PH2ADJC1
12 8 PH2ADJC2
13 9 PH2ADJC3
14 10 PH2ADJC4
15 11 PH2ADJC5
16 12 PH2ADJC6
17 13 OUT2DIVRSEL0
18 14 OUT2DIVRSEL1
19 15 OUT2DIVRSEL2
20 16 OUT2DIVRSEL3
21 17 OUT2DIVRSEL4
22 18 OUT2DIVRSEL5
23 19 OUT2DIVRSEL6
24 20 OUT2DIVSEL
25 21 HiSWINGLVPEC2
26 22 CMOSMODE2PX
27 23 CMOSMODE2PY
28 24 CMOSMODE2NX
29 25 CMOSMODE2NY
30 26 OUTBUFSEL2X
31 27 OUTBUFSEL2Y
Table 7. CDCE62005 Register 2 Bit Definitions
RELATED
BLOCK
DESCRIPTION/FUNCTION
Address 0
Address 1
Address 2
Address 3
Reference ^{Reference Divider Bit “0”}
Divider _{Reference Divider Bit “1”}
Used in Test Mode
Used in Test Mode
Output 2 OUTPUT MUX “2” Select. Selects the Signal driving Output Divider”2”
Output 2 ^{(X,Y) = 00: PRI_IN, 01:SEC_IN, 10:SMART_MUX, 11:VCO_CORE}
Output 2
Output 2
Output 2
Output 2 Coarse phase adjust select for output divider “2”
Output 2
Output 2
Output 2
Output 2
Output 2
Output 2
Output 2 OUTPUT DIVIDER “2” Ratio Select
Output 2
Output 2
Output 2
When set to “0”, the divider is disabled
Output 2 _{When set to “1”, the divider is enabled}
Output 2
High Swing LVPECL When set to “1” and Normal Swing when set to “0”
– If LVCMOS or LVDS is selected the Output swing will stay at the same level.
– If LVPECL buffer is selected the Output Swing will be 30% higher if this bit is set to “1”
and Normal LVPECL if it is set to “0”.
Output 2 LVCMOS mode select for OUTPUT “2” Positive Pin.
Output 2 ^{(X,Y)=00:Active, 10:Inverting, 11:Low, 01:3-State}
Output 2 LVCMOS mode select for OUTPUT “2” Negative Pin.
Output 2 ^{(X,Y)=00:Active, 10:Inverting, 11:Low, 01:3-State}
Output 2
OUTPUT TYPE
RAM BITS
22 23 24 25 26 27
LVPECL
00
0
0 01
Output 2
LVDS
LVCMOS
01
0
1
See Settings Above*
11
00
Output Disabled 0 1
0
1 10
* Use Description for Bits 22,23,24 and 25 for setting the LVCMOS Outputs
0
1
0
0
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s) :CDCE62005
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