CDCE62005 Datasheet, PDF (3/76 Pages) Texas Instruments – Five/Ten Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs

CDCE62005
www.ti.com........................................................................................................................................................................................... SCAS862 – NOVEMBER 2008
PACKAGE
The CDCE62005 is packaged in a 48-Pin Plastic Quad Flatpack Package with enhanced bottom thermal pad for
heat dissipation. The Texas Instruments Package Designator is: RGZ (S-PQFP-N48)
36
37
25
24
48
1
Top View
Not up to Scale
13
12
Figure 2. 48-Pin QFN Package Outline
PIN
NAME
VCC_OUT
VCC_AUXOUT
VCC1_PLL
VCC2_PLL
VCC_VCO
VCC_IN_PRI
VCC_IN_SEC
VCC_AUXIN
GND_VCO
GND
SPI_MISO
SPI_LE
SPI_CLK
SPI_MOSI
TEST_MODE
PIN FUNCTIONS
QFN
8, 11,
18, 21,
26, 29,
32
15
5
39, 42
34, 35
47
1
44
36
PAD
22
25
24
23
33
TYPE
Power 3.3V Supply for the Output Buffers
DESCRIPTION
Power 3.3V to Power the AUX_OUT circuitry
A. Power 3.3V PLL Supply Voltage for the PLL circuitry. (Filter Required)
A. Power 3.3V PLL Supply Voltage for the PLL circuitry. (Filter Required)
A. Power 3.3V VCO Input Buffer and Circuitry Supply Voltage. (Filter Required)
A. Power 3.3V References Input Buffer and Circuitry Supply Voltage.
A. Power 3.3V References Input Buffer and Circuitry Supply Voltage.
A. Power 3.3V Crystal Oscillator Input Circuitry.
Ground Ground that connects to VCO Ground. (VCO_GND is shorted to GND)
Ground Ground is on Thermal PAD. See Layout recommendation
OD In SPI Mode it is an Open Drain Output and it functions as a Master In Slave Out as a serial
Control Data Output to CDCE62005 .
I
LVCMOS input, control Latch Enable for Serial Programmable Interface (SPI), with Hysteresis in
SPI Mode. The input has an internal 150-kΩ pull-up resistor if left unconnected it will default to
logic level “1”.
I
LVCMOS input, serial Control Clock Input for the SPI bus interface, with Hysteresis. The input has
an internal 150-kΩ pull-up resistor if left unconnected it will default to logic level “1”.
I
LVCMOS input, Master Out Slave In as a serial Control Data Input to CDCE62005 for the SPI bus
interface. The input has an internal 150-kΩ pull-up resistor if left unconnected it will default to logic
level “1”.
I
This pin should be tied high or left unconnected.
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s) :CDCE62005
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