CDCE62005 Datasheet, PDF (38/76 Pages) Texas Instruments – Five/Ten Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs

CDCE62005
SCAS862 – NOVEMBER 2008........................................................................................................................................................................................... www.ti.com
INPUT BLOCK
The Input Block includes two Universal Input Buffers, an Auxiliary Input, and a Smart Multiplexer. The Input Block
drives three different clock signals onto the Internal Clock Distribution Bus: buffered versions of both the primary
and secondary inputs (PRI_IN and SEC_IN) and the output of the Smart Multiplexer.
Universal Input Buffers
LVPECL : 1500 MHz
LVDS : 800 MHz
LVCMOS : 250 MHz
PRI_IN
Register 6
12
Register 5
98610
SEC _ IN
1500 MHz
1500 MHz
Register 5
5432
REF _SEL
Auxiliary Input
Crystal : 2 MHz – 42 MHz
XTAL /
Single Ended : 2 MHz – 75 MHz AUX _IN
Smart MUX
Control
Register 0
10
Smart Multiplexer
/1:/2:HiZ
250 MHz
Register 1
10
/1:/2:HiZ
250 MHz
Smart
MUX 1
Reference Divider
/1 - /8
Register 3 Register 2
0 10
Smart
MUX2
Figure 23. CDCE62005 Input Block With References to Registers
38
Submit Documentation Feedback
Product Folder Link(s) :CDCE62005
Copyright © 2008, Texas Instruments Incorporated