CDCE62005 Datasheet, PDF (32/76 Pages) Texas Instruments – Five/Ten Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs

CDCE62005
SCAS862 – NOVEMBER 2008........................................................................................................................................................................................... www.ti.com
Device Registers: Register 5
SPI RAM BIT NAME
BIT BIT
0
A0
1
A1
2
A2
3
A3
4
0 INBUFSELX
5
1 INBUFSELY
6
2 PRISEL
7
3 SECSEL
8
4 AUXSEL
9
5 EECLKSEL
10
6 ACDCSEL
11
7 HYSTEN
12
8 PRI_TERMSEL
13
9 PRIINVBB
14 10 SECINVBB
15 11 FAILSAFE
16 12 RESERVED
17 13 RESERVED
18 14 SELINDIV0
19 15 SELINDIV1
20 16 SELINDIV2
21 17 SELINDIV3
22 18 SELINDIV4
23 19 SELINDIV5
24 20 SELINDIV6
25 21 SELINDIV7
26 22 LOCKW(0)
27 23 LOCKW(1)
28 24 LOCKW(2)
29 25 LOCKW(3)
30 26 LOCKDET
31 27 ADLOCK
Table 10. CDCE62005 Register 5 Bit Definitions
RELATED
BLOCK
INBUFSELX
INBUFSELY
Smart MUX
Smart MUX
Input Buffers
Input Buffers
Input Buffers
Input Buffers
Input Buffers
Input Buffers
--------
VCO Core
VCO Core
VCO Core
VCO Core
VCO Core
VCO Core
VCO Core
VCO Core
PLL Lock
PLL Lock
PLL Lock
DESCRIPTION/FUNCTION
Address 0
Address 1
Address 2
Address 3
Input Buffer Select (LVPECL,LVDS or LVCMOS)
XY(01 ) LVPECL, (11) LVDS, (00) LVCMOS- Input is Positive Pin
WHEN EECLKSEL = 1;
Bit (6,7,8) 100 – PRISEL, 010 – SECSEL , 001 – AUXSEL
110 – Auto Select ( PRI then SEC)
111 – Auto Select ( PRI then SEC and then AUX)
When EECLKSEL = 0, REF_SEL pin determines the Reference Input to the Smart Mux
circuitry.
If EEPROM Clock Select Input is set to “1” The Clock selections follows internal EEPROM
settings and ignores REF_SEL Pin status, when Set to “0” REF_SEL is used to control
the Mux, Auto Select Function is not available and AUXSEL is not available.
If Set to “1” DC Termination, If set to “0” AC Termination
If Set to “1” Input Buffers Hysteresis Enabled. It is not recommended that Hysteresis be
disabled.
If Set to “0” Primary Input Buffer Internal Termination Enabled
If set to “1” Primary Internal Termination circuitry Disabled
If Set to “1” Primary Input Negative Pin Biased with Internal VBB Voltage.
If Set to “1” Secondary Input Negative Pin Biased with Internal VBB Voltage
If Set to “1” Fail Safe is Enabled for all Input Buffers configured as LVDS, DC Coupling
only.
Must be set to “0”
Must be set to “0”
INPUT DIVIDER Settings
LOCKW(3:0): Lock-detect Window Width
= 0000 (narrow window),
= 0001,0010,0100,0101 …..
= 1110 (widest window)
= XX11 (RESERVED)
Number of coherent lock events. If set to “0” it triggers after the first lock detection if set to
“1” it triggers lock after 64 cycles of lock detections.
Selects Digital PLL_LOCK “0” ,Selects Analog PLL_LOCK “1”
1
0
1
0
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
32
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