CDCE62005 Datasheet, PDF (28/76 Pages) Texas Instruments – Five/Ten Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs

CDCE62005
SCAS862 – NOVEMBER 2008........................................................................................................................................................................................... www.ti.com
Device Registers: Register 1
SPI RA BIT NAME
BIT M
BIT
0
A0
1
A1
2
A2
3
A3
4 0 DIV2SECX
5 1 DIV2SECY
6 2 RESERVED
7 3 RESERVED
8 4 OUTMUX1SELX
9 5 OUTMUX1SELY
10 6 PH1ADJC0
11 7 PH1ADJC1
12 8 PH1ADJC2
13 9 PH1ADJC3
14 10 PH1ADJC4
15 11 PH1ADJC5
16 12 PH1ADJC6
17 13 OUT1DIVRSEL0
18 14 OUT1DIVRSEL1
19 15 OUT1DIVRSEL2
20 16 OUT1DIVRSEL3
21 17 OUT1DIVRSEL4
22 18 OUT1DIVRSEL5
23 19 OUT1DIVRSEL6
24 20 OUT1DIVSEL
25 21 HiSWINGLVPECL1
26 22 CMOSMODE1PX
27 23 CMOSMODE1PY
28 24 CMOSMODE1NX
29 25 CMOSMODE1NY
30 26 OUTBUFSEL1X
31 27 OUTBUFSEL1Y
Table 6. CDCE62005 Register 1 Bit Definitions
RELATED
BLOCK
DESCRIPTION/FUNCTION
Address 0
Address 1
Address 2
Address 3
Secondary ^{Pre-Divider Selection for the Secondary Reference}
Reference (X,Y)=00:3-state, 01:Divide by “1”, 10:Divide by “2”, 11:Reserved
Output 1
Output 1
Output 1
Output 1
Output 1
Output 1
Output 1
Output 1
Output 1
Output 1
Output 1
Output 1
Output 1
Output 1
Output 1
Output 1
Output 1
Output 1
Output 1
Output 1
Output 1
Output 1
Output 1
Output 1
Used in Test Mode
Used in Test Mode
OUTPUT MUX “1” Select. Selects the Signal driving Output Divider”1”
(X,Y) = 00: PRI_IN, 01:SEC_IN, 10:SMART_MUX, 11:VCO_CORE
Coarse phase adjust select for output divider “1”
OUTPUT DIVIDER “1” Ratio Select
When set to “0”, the divider is disabled
When set to “1”, the divider is enabled
High Swing LVPECL When set to “1” and Normal Swing when set to “0”
– If LVCMOS or LVDS is selected the Output swing will stay at the same level.
– If LVPECL buffer is selected the Output Swing will be 30% higher if this bit is set to “1”
and Normal LVPECL if it is set to “0”.
LVCMOS mode select for OUTPUT “1” Positive Pin.
(X,Y)=00:Active, 10:Inverting, 11:Low, 01:3-State
LVCMOS mode select for OUTPUT “1” Negative Pin.
(X,Y)=00:Active, 10:Inverting, 11:Low, 01:3-State
OUTPUT TYPE
RAM BITS
22 23 24 25 26 27
LVPECL
00
0 00 1
LVDS
01
0 11 1
LVCMOS
See Settings Above* 0 0
Output Disabled
01
0 11 0
* Use Description for Bits 22,23,24 and 25 for setting the LVCMOS Outputs
1
0
0
0
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
28
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