CDCE62005 Datasheet, PDF (44/76 Pages) Texas Instruments – Five/Ten Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs

CDCE62005
SCAS862 – NOVEMBER 2008........................................................................................................................................................................................... www.ti.com
Output Multiplexer Control
The Clock Divider Module receives the clock selected by the output multiplexer. The output multiplexer selects
from one of four clock sources available on the Internal Clock Distribution. For a description of PRI_IN, SEC_IN,
and SMART_MUX, see Figure 23. For a description of SYNTH, see Figure 33.
Table 20. CDCE62005 Output Multiplexer Control Settings
OUTPUT MULTIPLEXER CONTROL
Register n (n = 0,1,2,3,4)
OUTMUXnSELX
n.4
OUTMUXnSELY
n.5
0
0
0
1
1
0
1
1
CLOCK SOURCE SELECTED
PRI_IN
SEC_IN
SMART_MUX
SYNTH
Output Buffer Control
Each of the five output channels includes a programmable output buffer; supporting LVPECL, LVDS, and
LVCMOS modes. Table 21 lists the settings required to configure the CDCE62005 for each output type.
Registers 0 through 4 correspond to Output Channels 0 through 4 respectively.
Table 21. CDCE62005 Output Buffer Control Settings
OUTPUT BUFFER CONTROL
Register n (n = 0,1,2,3,4)
CMOSMODEnPX CMOSMODEnPY CMOSMODEnNX CMOSMODEnNY
n.22
n.23
n.24
n.25
0
0
0
0
0
1
0
1
See LVCMOS Output Buffer Configuration Settings
0
1
0
1
OUTBUFSELnX
n.26
0
1
0
1
OUTBUFSELnY
n.27
1
1
0
0
OUTPUT TYPE
LVPECL
LVDS
LVCMOS
OFF
Output Buffer Control – LVCMOS Configurations
A LVCMOS output configuration requires additional configuration data. In the single ended configuration, each
Output Channel provides a pair of outputs. The CDCE62005 supports four modes of operation for single ended
outputs as listed in Table 22.
Table 22. LVCMOS Output Buffer Configuration Settings
CMOSMODEnPX
n.22
X
X
X
X
0
0
1
1
OUTPUT BUFFER CONTROL – LVCMOS CONFIGURATION
Register n (n = 0,1,2,3,4)
CMOSMODEnPY CMOSMODEnNX CMOSMODEnNY OUTBUFSELnX
n.23
n.24
n.25
n.26
X
0
0
0
X
0
1
0
X
1
0
0
X
1
1
0
0
X
X
0
1
X
X
0
0
X
X
0
1
X
X
0
OUTBUFSELnY
n.27
0
0
0
0
0
0
0
0
Output
Type
Pin
Output Mode
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Negative
Negative
Negative
Negative
Positive
Positive
Positive
Positive
Active – Non-inverted
Hi-Z
Active – Non-inverted
Low
Active – Non-inverted
Hi-Z
Active – Non-inverted
Low
44
Submit Documentation Feedback
Product Folder Link(s) :CDCE62005
Copyright © 2008, Texas Instruments Incorporated