CDCE62005 Datasheet, PDF (42/76 Pages) Texas Instruments – Five/Ten Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs

CDCE62005
SCAS862 – NOVEMBER 2008........................................................................................................................................................................................... www.ti.com
Bit Name →
Register.Bit →
Table 18. CDCE62005 Pre-Divider Settings (continued)
Primary Pre-Divider
DIV2PRIY
0.1
DIV2PRIX
0.0
1
0
1
1
Divide Ratio
/1
Reserved
Bit Name →
Register.Bit →
Secondary Pre-Divider
DIV2SECY
1.1
DIV2SECX
1.0
1
0
1
1
Divide Ratio
/1
Reserved
The CDCE62005 provides a Reference Divider that divides the clock exiting the first multiplexer stage; thus
dividing the primary (PRI_IN) or the secondary input (SEC_IN).
Bit Name →
Register.Bit →
Table 19. CDCE62005 Reference Divider Settings
Reference Divider
REFDIV2
3.0
REFDIV1
2.1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
REFDIV0
2.0
0
1
0
1
0
1
0
1
Divide Ratio
/1
/2
/3
/4
/5
/6
/7
/8
Auxiliary Input Port
The auxiliary input on the CDCE62005 is designed to connect to an AT-Cut Crystal with a total load
capacitance(C_L) of 0 to 10pF. One side of the crystal connects to Ground while the other side connects to the
Auxiliary input of the device. The circuit works optimally between 20 to 40MHz but it can accept crystals from 2 to
42MHz.
Since the Auxiliary input operates between 0 and 2 V with a crystal, it can accept single-ended signals (e.g.
LVCMOS). Electrically, it is equivalent to an LVCMOS input buffer with 10pf of input capacitance.
C_L
8 pF
Figure 27. CDCE62005 Auxiliary Input Port
42
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