CDCE62005 Datasheet, PDF (4/76 Pages) Texas Instruments – Five/Ten Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs

CDCE62005
SCAS862 – NOVEMBER 2008........................................................................................................................................................................................... www.ti.com
PIN
NAME
REF_SEL
QFN
31
Power_Down
12
SYNC
AUX IN
AUX OUT
PRI REF+
PRI REF–
SEC REF+
SEC REF–
TESTOUTA
REG_CAP1
REG_CAP2
VBB
EXT_LFP
EXT_LFN
PLL_LOCK
U0P:U0N
U1P:U1N:
U2P:U2N
U3P:U3N
U4P:U4N
14
43
13
45
46
3
2
30
4
38
48
40
41
37
27, 28
19, 20
16,17
9, 10
6, 7
PIN FUNCTIONS (continued)
TYPE
DESCRIPTION
I
I
I
I
O
I
I
I
I
Analog
Analog
Analog
Analog
Analog
Analog
AI/O
O
If Auto Reference Select Mode is OFF this Pin acts as External Input Reference Select Pin;
The REF_SEL signal selects one of the two input clocks:
REF_SEL [1]: PRI_IN is selected; REF_SEL [0]: SEC_IN is selected;
The input has an internal 150-kΩ pull-up resistor if left unconnected it will default to logic level “1”.
If Auto Reference Select Mode in ON this Pin not used.
Active Low. Power down mode can be activated via this pin. See Table 14 for more details. The
input has an internal 150-kΩ pull-up resistor if left unconnected it will default to logic level “1”.
SPI_LE has to be HIGH in order for the rising edge of Power_Down signal to load the EEPROM.
Active Low. Sync mode can be activated via this pin. See Table 14 for more details. The input has
an internal 150-kΩ, pull-up resistor if left unconnected it will default to logic level “1”.
Auxiliary Input is a single ended input including an on-board oscillator circuit so that a crystal may
be connected.
Auxiliary Output LVCMOS level that can be programmed via SPI interface to be driven by Output 2
or Output 3.
Universal Input Buffer (LVPECL, LVDS, LVCMOS) positive input for the Primary Reference Clock,
Universal Input Buffer (LVPECL, LVDS) negative input for the Primary Reference Clock. In case of
LVCMOS signaling Ground this pin.
Universal Input Buffer (LVPECL, LVDS, LVCMOS) positive input for the Secondary Reference
Clock,
Universal Input Buffer (LVPECL, LVDS,) negative input for the Secondary Reference Clock. In
case of LVCMOS signaling Ground this pin.
Analog Test Point for Use for TI Internal Testing. Pull Down to GND Via a 1kΩs Resistor.
Capacitor for the internal Regulator. Connect to a 10uF Capacitor (Y5V)
Capacitor for the internal Regulator. Connect to a 10uF Capacitor (Y5V)
Capacitor for the internal termination Voltage. Connect to a 1uF Capacitor (Y5V)
External Loop Filter Input Positive
External Loop Filter Input Negative.
Output that indicates PLL Lock Status. See Figure 36.
The Main outputs of CDCE62005 are user definable and can be any combination of up to 5
LVPECL outputs, 5 LVDS outputs or up to 10 LVCMOS outputs. The outputs are selectable via
SPI interface. The power-up setting is EEPROM configurable.
4
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