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CDCE62005 Datasheet, PDF (21/76 Pages) Texas Instruments – Five/Ten Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs
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CDCE62005
www.ti.com........................................................................................................................................................................................... SCAS862 – NOVEMBER 2008
SPI CONTROL INTERFACE TIMING
t1
t4
t5
SPI _ CLK
SPI _ MOSI
Bit0
SPI _ LE
t2
t3
Bit1
Bit29
Bit30
Bit31
t7
t6
Figure 14. Timing Diagram for SPI Write Command
t4
t5
SPI _ CLK
SPI _ MOSI
SPI _ MISO
SPI _ LE
Bit30
t2
t3
Bit31
t7
t9
Bit0
Bit1
Bit2
t6
t8
Figure 15. Timing Diagram for SPI Read Command
fClock
t1
t2
t3
t4
t5
t6
t7
t8
SPI Bus Timing Characteristics
PARAMETER
Clock Frequency for the SPI_CLK
SPI_LE to SPI_CLK setup time
SPI_MOSI to SPI_CLK setup time
SPI_MOSI to SPI_CLK hold time
SPI_CLK high duration
SPI_CLK low duration
SPI_CLK to SPI_LE Setup time
SPI_LE Pulse Width
SPI_MISO to SPI_CLK Data Valid (First Valid Bit after LE)
MIN TYP MAX UNIT
20 MHz
10
ns
10
ns
10
ns
25
ns
25
ns
10
ns
20
ns
10
ns
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