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CDCE62005 Datasheet, PDF (27/76 Pages) Texas Instruments – Five/Ten Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs
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CDCE62005
www.ti.com........................................................................................................................................................................................... SCAS862 – NOVEMBER 2008
Device Registers: Register 0
SPI RAM BIT NAME
BIT BIT
0
A0
1
A1
2
A2
3
A3
4
0 DIV2PRIX
5
1 DIV2PRIY
6
2 RESERVED
7
3 RESERVED
8
4 OUTMUX0SELX
9
5 OUTMUX0SELY
10 6 PH0ADJC0
11 7 PH0ADJC1
12 8 PH0ADJC2
13 9 PH0ADJC3
14 10 PH0ADJC4
15 11 PH0ADJC5
16 12 PH0ADJC6
17 13 OUT0DIVRSEL0
18 14 OUT0DIVRSEL1
19 15 OUT0DIVRSEL2
20 16 OUT0DIVRSEL3
21 17 OUT0DIVRSEL4
22 18 OUT0DIVRSEL5
23 19 OUT0DIVRSEL6
24 20 OUT0DIVSEL
25 21 HiSWINGLVPECL0
26 22 CMOSMODE0PX
27 23 CMOSMODE0PY
28 24 CMOSMODE0NX
29 25 CMOSMODE0NY
30 26 OUTBUFSEL0X
31 27 OUTBUFSEL0Y
Table 5. CDCE62005 Register 0 Bit Definitions
RELATED
BLOCK
Primary
Reference
DESCRIPTION/FUNCTION
Address 0
Address 1
Address 2
Address 3
Pre-Divider Selection for the Primary Reference
(X,Y)=00:3-state, 01:Divide by “1”, 10:Divide by “2”, 11:Reserved
Output 0
Output 0
Output 0
Output 0
Output 0
Output 0
Output 0
Output 0
Output 0
Output 0
Output 0
Output 0
Output 0
Output 0
Output 0
Output 0
Output 0
Output 0
Output 0
Output 0
Output 0
Output 0
Output 0
Output 0
Used in Test Mode
Used in Test Mode
OUTPUT MUX “0” Select. Selects the Signal driving Output Divider”0”
(X,Y) = 00: PRI_IN, 01:SEC_IN, 10:SMART_MUX, 11:VCO_CORE
Coarse phase adjust select for output divider “0”
OUTPUT DIVIDER “0” Ratio Select
When set to “0”, the divider is disabled
When set to “1”, the divider is enabled
High Swing LVPECL When set to “1” and Normal Swing when set to “0”
– If LVCMOS or LVDS is selected the Output swing will stay at the same level.
– If LVPECL buffer is selected the Output Swing will be 30% higher if this bit is set to “1”
and Normal LVPECL if it is set to “0”.
LVCMOS mode select for OUTPUT “0” Positive Pin.
(X,Y)=00:Active, 10:Inverting, 11:Low, 01:3-State
LVCMOS mode select for OUTPUT “0” Negative Pin.
(X,Y)=00:Active, 10:Inverting, 11:Low, 01:3-State
OUTPUT TYPE
RAM BITS
22 23 24 25 26 27
LVPECL
00 0 0 0 1
LVDS
01 0 1 1 1
LVCMOS
See Settings Above* 0 0
Output Disabled
01 0 1 1 0
* Use Description for Bits 22,23,24 and 25 for setting the LVCMOS Outputs
0
0
0
0
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s) :CDCE62005
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